mirror of
https://github.com/AuroraWright/SafeA9LHInstaller.git
synced 2025-06-26 21:52:47 +00:00
434 lines
11 KiB
C
Executable File
434 lines
11 KiB
C
Executable File
/*
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* crypto.c
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*
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* Crypto libs from http://github.com/b1l1s/ctr
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*/
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#include "crypto.h"
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#include "memory.h"
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#include "fatfs/sdmmc/sdmmc.h"
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/****************************************************************
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* Crypto Libs
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****************************************************************/
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/* original version by megazig */
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#ifndef __thumb__
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#define BSWAP32(x) {\
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__asm__\
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(\
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"eor r1, %1, %1, ror #16\n\t"\
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"bic r1, r1, #0xFF0000\n\t"\
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"mov %0, %1, ror #8\n\t"\
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"eor %0, %0, r1, lsr #8\n\t"\
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:"=r"(x)\
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:"0"(x)\
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:"r1"\
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);\
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};
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#define ADD_u128_u32(u128_0, u128_1, u128_2, u128_3, u32_0) {\
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__asm__\
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(\
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"adds %0, %4\n\t"\
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"addcss %1, %1, #1\n\t"\
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"addcss %2, %2, #1\n\t"\
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"addcs %3, %3, #1\n\t"\
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: "+r"(u128_0), "+r"(u128_1), "+r"(u128_2), "+r"(u128_3)\
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: "r"(u32_0)\
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: "cc"\
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);\
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}
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#else
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#define BSWAP32(x) {x = __builtin_bswap32(x);}
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#define ADD_u128_u32(u128_0, u128_1, u128_2, u128_3, u32_0) {\
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__asm__\
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(\
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"mov r4, #0\n\t"\
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"add %0, %0, %4\n\t"\
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"adc %1, %1, r4\n\t"\
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"adc %2, %2, r4\n\t"\
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"adc %3, %3, r4\n\t"\
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: "+r"(u128_0), "+r"(u128_1), "+r"(u128_2), "+r"(u128_3)\
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: "r"(u32_0)\
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: "cc", "r4"\
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);\
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}
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#endif /*__thumb__*/
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static void aes_setkey(u8 keyslot, const void *key, u32 keyType, u32 mode)
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{
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if(keyslot <= 0x03) return; // Ignore TWL keys for now
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u32 *key32 = (u32 *)key;
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*REG_AESCNT = (*REG_AESCNT & ~(AES_CNT_INPUT_ENDIAN | AES_CNT_INPUT_ORDER)) | mode;
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*REG_AESKEYCNT = (*REG_AESKEYCNT >> 6 << 6) | keyslot | AES_KEYCNT_WRITE;
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REG_AESKEYFIFO[keyType] = key32[0];
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REG_AESKEYFIFO[keyType] = key32[1];
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REG_AESKEYFIFO[keyType] = key32[2];
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REG_AESKEYFIFO[keyType] = key32[3];
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}
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static void aes_use_keyslot(u8 keyslot)
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{
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if(keyslot > 0x3F)
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return;
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*REG_AESKEYSEL = keyslot;
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*REG_AESCNT = *REG_AESCNT | 0x04000000; /* mystery bit */
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}
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static void aes_setiv(const void *iv, u32 mode)
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{
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const u32 *iv32 = (const u32 *)iv;
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*REG_AESCNT = (*REG_AESCNT & ~(AES_CNT_INPUT_ENDIAN | AES_CNT_INPUT_ORDER)) | mode;
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// Word order for IV can't be changed in REG_AESCNT and always default to reversed
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if(mode & AES_INPUT_NORMAL)
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{
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REG_AESCTR[0] = iv32[3];
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REG_AESCTR[1] = iv32[2];
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REG_AESCTR[2] = iv32[1];
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REG_AESCTR[3] = iv32[0];
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}
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else
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{
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REG_AESCTR[0] = iv32[0];
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REG_AESCTR[1] = iv32[1];
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REG_AESCTR[2] = iv32[2];
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REG_AESCTR[3] = iv32[3];
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}
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}
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static void aes_advctr(void *ctr, u32 val, u32 mode)
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{
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u32 *ctr32 = (u32 *)ctr;
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int i;
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if(mode & AES_INPUT_BE)
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{
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for(i = 0; i < 4; ++i) // Endian swap
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BSWAP32(ctr32[i]);
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}
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if(mode & AES_INPUT_NORMAL)
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{
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ADD_u128_u32(ctr32[3], ctr32[2], ctr32[1], ctr32[0], val);
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}
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else
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{
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ADD_u128_u32(ctr32[0], ctr32[1], ctr32[2], ctr32[3], val);
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}
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if(mode & AES_INPUT_BE)
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{
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for(i = 0; i < 4; ++i) // Endian swap
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BSWAP32(ctr32[i]);
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}
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}
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static void aes_change_ctrmode(void *ctr, u32 fromMode, u32 toMode)
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{
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u32 *ctr32 = (u32 *)ctr;
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int i;
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if((fromMode ^ toMode) & AES_CNT_INPUT_ENDIAN)
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{
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for(i = 0; i < 4; ++i)
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BSWAP32(ctr32[i]);
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}
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if((fromMode ^ toMode) & AES_CNT_INPUT_ORDER)
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{
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u32 temp = ctr32[0];
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ctr32[0] = ctr32[3];
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ctr32[3] = temp;
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temp = ctr32[1];
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ctr32[1] = ctr32[2];
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ctr32[2] = temp;
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}
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}
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static void aes_batch(void *dst, const void *src, u32 blockCount)
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{
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*REG_AESBLKCNT = blockCount << 16;
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*REG_AESCNT |= AES_CNT_START;
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const u32 *src32 = (const u32 *)src;
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u32 *dst32 = (u32 *)dst;
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u32 wbc = blockCount;
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u32 rbc = blockCount;
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while(rbc)
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{
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if(wbc && ((*REG_AESCNT & 0x1F) <= 0xC)) // There's space for at least 4 ints
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{
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*REG_AESWRFIFO = *src32++;
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*REG_AESWRFIFO = *src32++;
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*REG_AESWRFIFO = *src32++;
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*REG_AESWRFIFO = *src32++;
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wbc--;
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}
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if(rbc && ((*REG_AESCNT & (0x1F << 0x5)) >= (0x4 << 0x5))) // At least 4 ints available for read
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{
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*dst32++ = *REG_AESRDFIFO;
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*dst32++ = *REG_AESRDFIFO;
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*dst32++ = *REG_AESRDFIFO;
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*dst32++ = *REG_AESRDFIFO;
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rbc--;
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}
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}
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}
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static void aes(void *dst, const void *src, u32 blockCount, void *iv, u32 mode, u32 ivMode)
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{
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*REG_AESCNT = mode |
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AES_CNT_INPUT_ORDER | AES_CNT_OUTPUT_ORDER |
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AES_CNT_INPUT_ENDIAN | AES_CNT_OUTPUT_ENDIAN |
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AES_CNT_FLUSH_READ | AES_CNT_FLUSH_WRITE;
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u32 blocks;
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while(blockCount != 0)
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{
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if((mode & AES_ALL_MODES) != AES_ECB_ENCRYPT_MODE
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&& (mode & AES_ALL_MODES) != AES_ECB_DECRYPT_MODE)
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aes_setiv(iv, ivMode);
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blocks = (blockCount >= 0xFFFF) ? 0xFFFF : blockCount;
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// Save the last block for the next decryption CBC batch's iv
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if((mode & AES_ALL_MODES) == AES_CBC_DECRYPT_MODE)
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{
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memcpy(iv, src + (blocks - 1) * AES_BLOCK_SIZE, AES_BLOCK_SIZE);
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aes_change_ctrmode(iv, AES_INPUT_BE | AES_INPUT_NORMAL, ivMode);
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}
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// Process the current batch
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aes_batch(dst, src, blocks);
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// Save the last block for the next encryption CBC batch's iv
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if((mode & AES_ALL_MODES) == AES_CBC_ENCRYPT_MODE)
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{
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memcpy(iv, dst + (blocks - 1) * AES_BLOCK_SIZE, AES_BLOCK_SIZE);
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aes_change_ctrmode(iv, AES_INPUT_BE | AES_INPUT_NORMAL, ivMode);
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}
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// Advance counter for CTR mode
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else if((mode & AES_ALL_MODES) == AES_CTR_MODE)
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aes_advctr(iv, blocks, ivMode);
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src += blocks * AES_BLOCK_SIZE;
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dst += blocks * AES_BLOCK_SIZE;
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blockCount -= blocks;
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}
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}
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void sha_wait_idle()
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{
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while(*REG_SHA_CNT & 1);
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}
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void sha(void *res, const void *src, u32 size, u32 mode)
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{
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sha_wait_idle();
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*REG_SHA_CNT = mode | SHA_CNT_OUTPUT_ENDIAN | SHA_NORMAL_ROUND;
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const u32 *src32 = (const u32 *)src;
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int i;
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while(size >= 0x40)
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{
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sha_wait_idle();
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for(i = 0; i < 4; ++i)
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{
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*REG_SHA_INFIFO = *src32++;
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*REG_SHA_INFIFO = *src32++;
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*REG_SHA_INFIFO = *src32++;
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*REG_SHA_INFIFO = *src32++;
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}
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size -= 0x40;
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}
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sha_wait_idle();
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memcpy((void *)REG_SHA_INFIFO, src32, size);
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*REG_SHA_CNT = (*REG_SHA_CNT & ~SHA_NORMAL_ROUND) | SHA_FINAL_ROUND;
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while(*REG_SHA_CNT & SHA_FINAL_ROUND);
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sha_wait_idle();
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u32 hashSize = SHA_256_HASH_SIZE;
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if(mode == SHA_224_MODE)
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hashSize = SHA_224_HASH_SIZE;
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else if(mode == SHA_1_MODE)
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hashSize = SHA_1_HASH_SIZE;
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memcpy(res, (void *)REG_SHA_HASH, hashSize);
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}
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/****************************************************************
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* Nand/FIRM Crypto stuff
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****************************************************************/
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static u8 nandSlot, nandCTR[0x10];
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static u32 fatStart;
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const u8 key2s[3][0x10] = {
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{0x42, 0x3F, 0x81, 0x7A, 0x23, 0x52, 0x58, 0x31, 0x6E, 0x75, 0x8E, 0x3A, 0x39, 0x43, 0x2E, 0xD0},
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{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3B, 0xF5, 0xF6},
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{0x65, 0x29, 0x3E, 0x12, 0x56, 0x0C, 0x0B, 0xD1, 0xDD, 0xB5, 0x63, 0x1C, 0xB6, 0xD9, 0x52, 0x75}
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};
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//Get Nand CTR key
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void getNandCTR(void)
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{
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u8 cid[0x10];
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u8 shaSum[0x20];
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sdmmc_get_cid(1, (u32 *)cid);
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sha(shaSum, cid, 0x10, SHA_256_MODE);
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memcpy(nandCTR, shaSum, 0x10);
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}
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//Initialize the CTRNAND crypto
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void ctrNandInit(void)
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{
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getNandCTR();
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if(console)
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{
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u8 keyY0x5[0x10] = {0x4D, 0x80, 0x4F, 0x4E, 0x99, 0x90, 0x19, 0x46, 0x13, 0xA2, 0x04, 0xAC, 0x58, 0x44, 0x60, 0xBE};
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aes_setkey(0x05, keyY0x5, AES_KEYY, AES_INPUT_BE | AES_INPUT_NORMAL);
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nandSlot = 0x05;
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fatStart = 0x5CAD7;
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}
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else
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{
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nandSlot = 0x04;
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fatStart = 0x5CAE5;
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}
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}
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//Read and decrypt from CTRNAND
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u32 ctrNandRead(u32 sector, u32 sectorCount, u8 *outbuf)
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{
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u8 tmpCTR[0x10];
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memcpy(tmpCTR, nandCTR, 0x10);
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aes_advctr(tmpCTR, ((sector + fatStart) * 0x200) / AES_BLOCK_SIZE, AES_INPUT_BE | AES_INPUT_NORMAL);
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//Read
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u32 result = sdmmc_nand_readsectors(sector + fatStart, sectorCount, outbuf);
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//Decrypt
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aes_use_keyslot(nandSlot);
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aes(outbuf, outbuf, sectorCount * 0x200 / AES_BLOCK_SIZE, tmpCTR, AES_CTR_MODE, AES_INPUT_BE | AES_INPUT_NORMAL);
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return result;
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}
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//Read and decrypt from the FIRM0 partition on NAND
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void readFirm0(u8 *outbuf, u32 size)
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{
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u8 CTRtmp[0x10];
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memcpy(CTRtmp, nandCTR, 0x10);
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//Read FIRM0 data
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sdmmc_nand_readsectors(0x0B130000 / 0x200, size / 0x200, outbuf);
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//Decrypt
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aes_advctr(CTRtmp, 0x0B130000 / 0x10, AES_INPUT_BE | AES_INPUT_NORMAL);
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aes_use_keyslot(0x06);
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aes(outbuf, outbuf, size / AES_BLOCK_SIZE, CTRtmp, AES_CTR_MODE, AES_INPUT_BE | AES_INPUT_NORMAL);
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}
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//Encrypt and write a FIRM partition to NAND
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void writeFirm(u8 *inbuf, u32 firm, u32 size)
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{
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u32 offset = firm ? 0x0B530000 : 0x0B130000;
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u8 CTRtmp[0x10];
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memcpy(CTRtmp, nandCTR, 0x10);
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//Encrypt FIRM data
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aes_advctr(CTRtmp, offset / 0x10, AES_INPUT_BE | AES_INPUT_NORMAL);
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aes_use_keyslot(0x06);
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aes(inbuf, inbuf, size / AES_BLOCK_SIZE, CTRtmp, AES_CTR_MODE, AES_INPUT_BE | AES_INPUT_NORMAL);
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//Write to NAND
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sdmmc_nand_writesectors(offset / 0x200, size / 0x200, inbuf);
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}
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//Setup keyslot 0x11 for key sector de/encryption
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void setupKeyslot0x11(u32 a9lhBoot, const void *otp)
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{
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u8 shasum[0x20];
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u8 keyX[0x10];
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u8 keyY[0x10];
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//If booting via A9LH, use the leftover contents of the SHA register
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if(a9lhBoot) memcpy((void *)shasum, (void *)REG_SHA_HASH, 0x20);
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//Else calculate the otp.bin hash
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else sha(shasum, otp, 0x90, SHA_256_MODE);
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//Set keyX and keyY
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memcpy(keyX, shasum, 0x10);
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memcpy(keyY, shasum + 0x10, 0x10);
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aes_setkey(0x11, keyX, AES_KEYX, AES_INPUT_BE | AES_INPUT_NORMAL);
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aes_setkey(0x11, keyY, AES_KEYY, AES_INPUT_BE | AES_INPUT_NORMAL);
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}
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//Generate and encrypt an A9LH key sector
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void generateSector(u8 *keySector, u32 mode)
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{
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//Inject key2
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memcpy(keySector + 0x10, mode ? key2s[0] : key2s[2], 0x10);
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//Encrypt key sector
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aes_use_keyslot(0x11);
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for(u32 i = 0; i < 32; i++)
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aes(keySector + (0x10 * i), keySector + (0x10 * i), 1, NULL, AES_ECB_ENCRYPT_MODE, 0);
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}
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//Read and decrypt the NAND key sector
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void getSector(u8 *keySector)
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{
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//Read keysector from NAND
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sdmmc_nand_readsectors(0x96, 1, keySector);
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//Decrypt key sector
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aes_use_keyslot(0x11);
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for(u32 i = 0; i < 32; i++)
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aes(keySector + (0x10 * i), keySector + (0x10 * i), 1, NULL, AES_ECB_DECRYPT_MODE, 0);
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}
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//Check SHA256 hash
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u32 verifyHash(const void *data, u32 size, const u8 *hash)
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{
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u8 shasum[0x20];
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sha(shasum, data, size, SHA_256_MODE);
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return memcmp(shasum, hash, 0x20) == 0;
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}
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//Decrypt a FIRM ExeFS
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u32 decryptExeFs(u8 *inbuf)
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{
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u8 *exeFsOffset = inbuf + *(u32 *)(inbuf + 0x1A0) * 0x200;
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u32 exeFsSize = *(u32 *)(inbuf + 0x1A4) * 0x200;
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u8 ncchCTR[0x10] = {0};
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for(u32 i = 0; i < 8; i++)
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ncchCTR[7 - i] = *(inbuf + 0x108 + i);
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ncchCTR[8] = 2;
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aes_setkey(0x2C, inbuf, AES_KEYY, AES_INPUT_BE | AES_INPUT_NORMAL);
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aes_setiv(ncchCTR, AES_INPUT_BE | AES_INPUT_NORMAL);
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aes_use_keyslot(0x2C);
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aes(inbuf - 0x200, exeFsOffset, exeFsSize / AES_BLOCK_SIZE, ncchCTR, AES_CTR_MODE, AES_INPUT_BE | AES_INPUT_NORMAL);
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return exeFsSize - 0x200;
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} |