gnmmarechal/SafeA9LHInstaller
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Aurora 2016-11-26 00:53:07 +01:00
parent 5d1c717cb4
commit c77746f383
2 changed files with 10 additions and 1 deletions
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2
linker.ld
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@ -5,7 +5,7 @@ SECTIONS
.text.start : { *(.text.start) } .text.start : { *(.text.start) }
.text : { *(.text) } .text : { *(.text) }
.data : { *(.data) } .data : { *(.data) }
.bss : { *(.bss COMMON) } .bss : { __bss_start = .; *(.bss COMMON) } __bss_end = .;
.rodata : { *(.rodata) } .rodata : { *(.rodata) }
. = ALIGN(4); . = ALIGN(4);
} }

9
source/start.s
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@ -77,6 +77,15 @@ start:
mcr p15, 0, r8, c2, c0, 0 @ Data cacheable 0, 2, 4 mcr p15, 0, r8, c2, c0, 0 @ Data cacheable 0, 2, 4
mcr p15, 0, r8, c2, c0, 1 @ Inst cacheable 0, 2, 4 mcr p15, 0, r8, c2, c0, 1 @ Inst cacheable 0, 2, 4
@ Clear BSS
ldr r0, =__bss_start
ldr r1, =__bss_end
mov r2, #0
clear_bss_loop:
str r2, [r0], #4
cmp r0, r1
blo clear_bss_loop
@ Enable caches / MPU / ITCM @ Enable caches / MPU / ITCM
mrc p15, 0, r0, c1, c0, 0 @ read control register mrc p15, 0, r0, c1, c0, 0 @ read control register
orr r0, r0, #(1<<18) @ - ITCM enable orr r0, r0, #(1<<18) @ - ITCM enable