From bc97bc8af116723f5cb6572accf702af55fb5aad Mon Sep 17 00:00:00 2001 From: Aurora Date: Thu, 9 Jun 2016 15:37:45 +0200 Subject: [PATCH] Fix issue in the start.s --- source/start.s | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/source/start.s b/source/start.s index 83de9b4..52f88b9 100644 --- a/source/start.s +++ b/source/start.s @@ -19,7 +19,7 @@ _start: ldr r5, =0x20000037 @ 20000000 256M | fcram (O3DS / N3DS) ldr r6, =0x1FF00027 @ 1FF00000 1M | dsp / axi wram ldr r7, =0x1800002D @ 18000000 8M | vram (+ 2MB) - mov r8, #0x25 + mov r8, #0x29 mcr p15, 0, r0, c6, c0, 0 mcr p15, 0, r1, c6, c1, 0 mcr p15, 0, r2, c6, c2, 0 @@ -28,9 +28,9 @@ _start: mcr p15, 0, r5, c6, c5, 0 mcr p15, 0, r6, c6, c6, 0 mcr p15, 0, r7, c6, c7, 0 - mcr p15, 0, r8, c3, c0, 0 @ Write bufferable 0, 2, 5 - mcr p15, 0, r8, c2, c0, 0 @ Data cacheable 0, 2, 5 - mcr p15, 0, r8, c2, c0, 1 @ Inst cacheable 0, 2, 5 + mcr p15, 0, r8, c3, c0, 0 @ Write bufferable 0, 3, 5 + mcr p15, 0, r8, c2, c0, 0 @ Data cacheable 0, 3, 5 + mcr p15, 0, r8, c2, c0, 1 @ Inst cacheable 0, 3, 5 @ Enable caches mrc p15, 0, r0, c1, c0, 0 @ read control register