forked from Mirror/GodMode9
30f0b004c2
- properly performs gpu/backlight reset - nukes vram so the initrd had to be moved to arm9 memory, and have its size (at least temporarily) limited to 256k
187 lines
8.3 KiB
C
187 lines
8.3 KiB
C
/*
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* This file is part of GodMode9
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* Copyright (C) 2017-2019 Wolfvak
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <types.h>
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#define VBLANK_INTERRUPT (0x2A)
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enum
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{
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PDN_GPU_CNT_RST_REGS = 1u, // And more?
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PDN_GPU_CNT_RST_PSC = 1u<<1, // ?
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PDN_GPU_CNT_RST_GEOSHADER = 1u<<2, // ?
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PDN_GPU_CNT_RST_RASTERIZER = 1u<<3, // ?
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PDN_GPU_CNT_RST_PPF = 1u<<4,
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PDN_GPU_CNT_RST_PDC = 1u<<5, // ?
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PDN_GPU_CNT_RST_PDC2 = 1u<<6, // Maybe pixel pipeline or so?
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PDN_GPU_CNT_RST_ALL = (PDN_GPU_CNT_RST_PDC2<<1) - 1
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};
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typedef enum
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{
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GFX_RGBA8 = 0, ///< RGBA8. (4 bytes)
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GFX_BGR8 = 1, ///< BGR8. (3 bytes)
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GFX_RGB565 = 2, ///< RGB565. (2 bytes)
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GFX_RGB5A1 = 3, ///< RGB5A1. (2 bytes)
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GFX_RGBA4 = 4 ///< RGBA4. (2 bytes)
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} GfxFbFmt;
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typedef enum
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{
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GFX_EVENT_PSC0 = 0u,
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GFX_EVENT_PSC1 = 1u,
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GFX_EVENT_PDC0 = 2u,
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GFX_EVENT_PDC1 = 3u,
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GFX_EVENT_PPF = 4u,
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GFX_EVENT_P3D = 5u
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} GfxEvent;
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typedef enum
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{
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GFX_BLIGHT_BOT = 1u<<2,
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GFX_BLIGHT_TOP = 1u<<4,
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GFX_BLIGHT_BOTH = GFX_BLIGHT_TOP | GFX_BLIGHT_BOT
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} GfxBlight;
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#define REG_CFG11_GPUPROT *((vu16*)(0x10140140))
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#define REG_PDN_GPU_CNT *((vu32*)(0x10141200))
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#define PDN_GPU_CNT_CLK_E (1u<<16)
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#define PDN_VRAM_CNT_CLK_E (1u)
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#define GX_REGS_BASE (0x10400000)
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#define REG_GX_GPU_CLK *((vu32*)(GX_REGS_BASE + 0x0004)) // ?
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// PSC (memory fill) regs.
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#define REG_GX_PSC_FILL0_S_ADDR *((vu32*)(GX_REGS_BASE + 0x0010)) // Start address
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#define REG_GX_PSC_FILL0_E_ADDR *((vu32*)(GX_REGS_BASE + 0x0014)) // End address
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#define REG_GX_PSC_FILL0_VAL *((vu32*)(GX_REGS_BASE + 0x0018)) // Fill value
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#define REG_GX_PSC_FILL0_CNT *((vu32*)(GX_REGS_BASE + 0x001C))
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#define REG_GX_PSC_FILL1_S_ADDR *((vu32*)(GX_REGS_BASE + 0x0020))
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#define REG_GX_PSC_FILL1_E_ADDR *((vu32*)(GX_REGS_BASE + 0x0024))
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#define REG_GX_PSC_FILL1_VAL *((vu32*)(GX_REGS_BASE + 0x0028))
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#define REG_GX_PSC_FILL1_CNT *((vu32*)(GX_REGS_BASE + 0x002C))
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#define REG_GX_PSC_VRAM *((vu32*)(GX_REGS_BASE + 0x0030)) // gsp mudule only changes bit 8-11.
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#define REG_GX_PSC_STAT *((vu32*)(GX_REGS_BASE + 0x0034))
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// PDC0/1 regs see lcd.h.
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// PPF (transfer engine) regs.
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#define REG_GX_PPF_IN_ADDR *((vu32*)(GX_REGS_BASE + 0x0C00))
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#define REG_GX_PPF_OUT_ADDR *((vu32*)(GX_REGS_BASE + 0x0C04))
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#define REG_GX_PPF_DT_OUTDIM *((vu32*)(GX_REGS_BASE + 0x0C08)) // Display transfer output dimensions.
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#define REG_GX_PPF_DT_INDIM *((vu32*)(GX_REGS_BASE + 0x0C0C)) // Display transfer input dimensions.
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#define REG_GX_PPF_FlAGS *((vu32*)(GX_REGS_BASE + 0x0C10))
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#define REG_GX_PPF_UNK14 *((vu32*)(GX_REGS_BASE + 0x0C14)) // Transfer interval?
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#define REG_GX_PPF_CNT *((vu32*)(GX_REGS_BASE + 0x0C18))
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#define REG_GX_PPF_IRQ_POS *((vu32*)(GX_REGS_BASE + 0x0C1C)) // ?
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#define REG_GX_PPF_LEN *((vu32*)(GX_REGS_BASE + 0x0C20)) // Texture copy size in bytes.
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#define REG_GX_PPF_TC_INDIM *((vu32*)(GX_REGS_BASE + 0x0C24)) // Texture copy input width and gap in 16 byte units.
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#define REG_GX_PPF_TC_OUTDIM *((vu32*)(GX_REGS_BASE + 0x0C28)) // Texture copy output width and gap in 16 byte units.
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// P3D (GPU internal) regs. See gpu_regs.h.
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#define REG_GX_P3D(reg) *((vu32*)(GX_REGS_BASE + 0x1000 + ((reg) * 4)))
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// LCD/ABL regs.
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#define LCD_REGS_BASE (0x10202000)
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#define REG_LCD_PARALLAX_CNT *((vu32*)(LCD_REGS_BASE + 0x000)) // Controls PWM for the parallax barrier?
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#define REG_LCD_PARALLAX_PWM *((vu32*)(LCD_REGS_BASE + 0x004)) // Frequency/other PWM stuff maybe?
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#define REG_LCD_UNK00C *((vu32*)(LCD_REGS_BASE + 0x00C)) // Wtf is "FIX"?
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#define REG_LCD_RST *((vu32*)(LCD_REGS_BASE + 0x014)) // Reset active low.
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#define REG_LCD_ABL0_CNT *((vu32*)(LCD_REGS_BASE + 0x200)) // Bit 0 enables ABL aka power saving mode.
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#define REG_LCD_ABL0_FILL *((vu32*)(LCD_REGS_BASE + 0x204))
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#define REG_LCD_ABL0_LIGHT *((vu32*)(LCD_REGS_BASE + 0x240))
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#define REG_LCD_ABL0_LIGHT_PWM *((vu32*)(LCD_REGS_BASE + 0x244))
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#define REG_LCD_ABL1_CNT *((vu32*)(LCD_REGS_BASE + 0xA00)) // Bit 0 enables ABL aka power saving mode.
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#define REG_LCD_ABL1_FILL *((vu32*)(LCD_REGS_BASE + 0xA04))
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#define REG_LCD_ABL1_LIGHT *((vu32*)(LCD_REGS_BASE + 0xA40))
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#define REG_LCD_ABL1_LIGHT_PWM *((vu32*)(LCD_REGS_BASE + 0xA44))
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// Technically these regs belong in gx.h but they are used for LCD configuration so...
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// Pitfall warning: The 3DS LCDs are physically rotated 90° CCW.
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// PDC0 (top screen display controller) regs.
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#define REG_LCD_PDC0_HTOTAL *((vu32*)(GX_REGS_BASE + 0x400))
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#define REG_LCD_PDC0_VTOTAL *((vu32*)(GX_REGS_BASE + 0x424))
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#define REG_LCD_PDC0_HPOS *((const vu32*)(GX_REGS_BASE + 0x450))
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#define REG_LCD_PDC0_VPOS *((const vu32*)(GX_REGS_BASE + 0x454))
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#define REG_LCD_PDC0_FB_A1 *((vu32*)(GX_REGS_BASE + 0x468))
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#define REG_LCD_PDC0_FB_A2 *((vu32*)(GX_REGS_BASE + 0x46C))
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#define REG_LCD_PDC0_FMT *((vu32*)(GX_REGS_BASE + 0x470))
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#define REG_LCD_PDC0_CNT *((vu32*)(GX_REGS_BASE + 0x474))
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#define REG_LCD_PDC0_SWAP *((vu32*)(GX_REGS_BASE + 0x478))
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#define REG_LCD_PDC0_STAT *((const vu32*)(GX_REGS_BASE + 0x47C))
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#define REG_LCD_PDC0_GTBL_IDX *((vu32*)(GX_REGS_BASE + 0x480)) // Gamma table index.
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#define REG_LCD_PDC0_GTBL_FIFO *((vu32*)(GX_REGS_BASE + 0x484)) // Gamma table FIFO.
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#define REG_LCD_PDC0_STRIDE *((vu32*)(GX_REGS_BASE + 0x490))
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#define REG_LCD_PDC0_FB_B1 *((vu32*)(GX_REGS_BASE + 0x494))
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#define REG_LCD_PDC0_FB_B2 *((vu32*)(GX_REGS_BASE + 0x498))
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// PDC1 (bottom screen display controller) regs.
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#define REG_LCD_PDC1_HTOTAL *((vu32*)(GX_REGS_BASE + 0x500))
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#define REG_LCD_PDC1_VTOTAL *((vu32*)(GX_REGS_BASE + 0x524))
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#define REG_LCD_PDC1_HPOS *((const vu32*)(GX_REGS_BASE + 0x550))
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#define REG_LCD_PDC1_VPOS *((const vu32*)(GX_REGS_BASE + 0x554))
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#define REG_LCD_PDC1_FB_A1 *((vu32*)(GX_REGS_BASE + 0x568))
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#define REG_LCD_PDC1_FB_A2 *((vu32*)(GX_REGS_BASE + 0x56C))
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#define REG_LCD_PDC1_FMT *((vu32*)(GX_REGS_BASE + 0x570))
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#define REG_LCD_PDC1_CNT *((vu32*)(GX_REGS_BASE + 0x574))
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#define REG_LCD_PDC1_SWAP *((vu32*)(GX_REGS_BASE + 0x578))
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#define REG_LCD_PDC1_STAT *((const vu32*)(GX_REGS_BASE + 0x57C))
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#define REG_LCD_PDC1_GTBL_IDX *((vu32*)(GX_REGS_BASE + 0x580)) // Gamma table index.
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#define REG_LCD_PDC1_GTBL_FIFO *((vu32*)(GX_REGS_BASE + 0x584)) // Gamma table FIFO.
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#define REG_LCD_PDC1_STRIDE *((vu32*)(GX_REGS_BASE + 0x590))
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#define REG_LCD_PDC1_FB_B1 *((vu32*)(GX_REGS_BASE + 0x594))
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#define REG_LCD_PDC1_FB_B2 *((vu32*)(GX_REGS_BASE + 0x598))
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// REG_LCD_PDC_CNT
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#define PDC_CNT_E (1u)
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#define PDC_CNT_I_MASK_H (1u<<8) // Disables H(Blank?) IRQs.
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#define PDC_CNT_I_MASK_V (1u<<9) // Disables VBlank IRQs.
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#define PDC_CNT_I_MASK_ERR (1u<<10) // Disables error IRQs. What kind of errors?
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#define PDC_CNT_OUT_E (1u<<16) // Output enable?
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// REG_LCD_PDC_SWAP
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// Masks
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#define PDC_SWAP_NEXT (1u) // Next framebuffer.
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#define PDC_SWAP_CUR (1u<<4) // Currently displaying framebuffer?
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// Bits
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#define PDC_SWAP_RST_FIFO (1u<<8) // Which FIFO?
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#define PDC_SWAP_I_H (1u<<16) // H(Blank?) IRQ bit.
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#define PDC_SWAP_I_V (1u<<17) // VBlank IRQ bit.
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#define PDC_SWAP_I_ERR (1u<<18) // Error IRQ bit?
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#define PDC_SWAP_I_ALL (PDC_SWAP_I_ERR | PDC_SWAP_I_V | PDC_SWAP_I_H)
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unsigned GFX_init(GfxFbFmt mode);
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void GFX_setForceBlack(bool top, bool bot);
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void GFX_powerOnBacklights(GfxBlight mask);
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void GFX_powerOffBacklights(GfxBlight mask);
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u8 GFX_getBrightness(void);
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void GFX_setBrightness(u8 top, u8 bot);
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