forked from Mirror/GodMode9
165 lines
4.0 KiB
ArmAsm
165 lines
4.0 KiB
ArmAsm
.section .text.start
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.align 4
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.arm
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#include <arm.h>
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#include <brf.h>
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#include <entrypoints.h>
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#include "memmap.h"
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.global _start
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_start:
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@ Disable interrupts
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msr cpsr_c, #(SR_SVC_MODE | SR_NOINT)
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@ Preserve boot registers
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mov r8, r0
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mov r9, r1
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mov r10, r2
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@mov r11, r3 @ unnecessary for now
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@ Clear bss
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ldr r0, =__bss_start
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ldr r1, =__bss_end
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mov r2, #0
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.LBSS_Clear:
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cmp r0, r1
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strlo r2, [r0], #4
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blo .LBSS_Clear
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ldr r0, =BRF_WB_INV_DCACHE
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blx r0 @ Writeback & Invalidate Data Cache
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ldr r0, =BRF_INVALIDATE_ICACHE
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blx r0 @ Invalidate Instruction Cache
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@ Disable caches / TCMs / MPU
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ldr r1, =(CR_MPU | CR_CACHES | CR_DTCM | CR_ITCM | CR_TCM_LOAD)
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r1
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mcr p15, 0, r0, c1, c0, 0
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@ Set access permissions
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ldr r0, =0x11111115 @ RO data access for BootROM, RW otherwise
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ldr r1, =0x00505005 @ Can only execute code from ARM9 RAM, FCRAM and BootROM
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mcr p15, 0, r0, c5, c0, 2
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mcr p15, 0, r1, c5, c0, 3
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@ Set MPU regions and cache settings
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ldr r0, =__mpu_regions
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ldmia r0, {r0-r7}
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mcr p15, 0, r0, c6, c0, 0
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mcr p15, 0, r1, c6, c1, 0
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mcr p15, 0, r2, c6, c2, 0
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mcr p15, 0, r3, c6, c3, 0
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mcr p15, 0, r4, c6, c4, 0
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mcr p15, 0, r5, c6, c5, 0
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mcr p15, 0, r6, c6, c6, 0
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mcr p15, 0, r7, c6, c7, 0
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mov r0, #0b10101000 @ enable write buffer for VRAM
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mcr p15, 0, r0, c3, c0, 0 @ Write bufferable
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mov r0, #0b00101000
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mcr p15, 0, r0, c2, c0, 0 @ Data cacheable
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mcr p15, 0, r0, c2, c0, 1 @ Inst cacheable
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@ Configure TCMs
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ldr r0, =0x3000800A
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ldr r1, =0x00000024
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mcr p15, 0, r0, c9, c1, 0 @ DTCM
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mcr p15, 0, r1, c9, c1, 1 @ ITCM
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@ Setup heap
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ldr r0, =fake_heap_start
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ldr r1, =__HEAP_ADDR
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str r1, [r0]
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ldr r0, =fake_heap_end
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ldr r1, =__HEAP_END
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str r1, [r0]
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@ Install exception handlers
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ldr r0, =__vectors_lma
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ldr r1, =__vectors_len
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ldr r2, =XRQ_Start
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add r1, r0, r1
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.LXRQ_Install:
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cmp r0, r1
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ldrlo r3, [r0], #4
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strlo r3, [r2], #4
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blo .LXRQ_Install
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@ Enable caches / TCMs / select high exception vectors
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ldr r1, =(CR_MPU | CR_CACHES | CR_ITCM | CR_DTCM | CR_ALT_VECTORS)
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r1
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mcr p15, 0, r0, c1, c0, 0
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@ Switch to system mode, disable interrupts, setup application stack
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msr cpsr_c, #(SR_SYS_MODE | SR_NOINT)
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ldr sp, =__STACK_TOP
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@ Check entrypoints
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@ assume by default that the entrypoint
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@ cant be detected and fix up if necessary
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mov r0, #0
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mov r1, #0
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ldr r2, =ENTRY_UNKNOWN
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@ returning from main will trigger a prefetch abort
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mov lr, #0
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@ B9S
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@ if (R2 & 0xFFFF) == 0xBEEF
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ldr r3, =0xBEEF
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lsl r2, r10, #16
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cmp r3, r2, lsr #16
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moveq r0, r8
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moveq r1, r9
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ldreq r2, =ENTRY_B9S
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ldreq pc, =main
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@ ntrboot
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@ if ([0x1FFFE010] | [0x1FFFE014]) == 0
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@ && ([0x1FFFE00C] & 0xFF00FF00) == 0x02000000
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ldr r3, =0x1FFFE010
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ldrd r4, r5, [r3]
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orrs r4, r4, r5
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ldreq r4, [r3, #-4]
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ldreq r5, =0xFF00FF00
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andeq r4, r4, r5
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cmpeq r4, #0x02000000
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ldreq r2, =ENTRY_NTRBOOT
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ldreq pc, =main
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@ nandboot
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@ if ([0x1FFFE010] | [0x1FFFE014]) != 0
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@ && ([0x1FFFE00C] & 0xFF) == 0
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ldrd r4, r5, [r3]
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orrs r4, r4, r5
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ldreq pc, =main
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ldrb r4, [r3, #-4]
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cmp r4, #0
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ldreq r2, =ENTRY_NANDBOOT
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@ unconditionally branch into the main C function
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@ if no entrypoint was detected
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@ R2 will be ENTRY_UNKNOWN
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ldr pc, =main
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__mpu_regions:
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.word 0xFFFF001F @ FFFF0000 64k | bootrom (unprotected / protected)
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.word 0x3000801B @ 30008000 16k | dtcm
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.word 0x01FF801D @ 01FF8000 32k | itcm (+ mirrors)
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.word 0x08000029 @ 08000000 2M | arm9 mem (O3DS / N3DS)
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.word 0x10000029 @ 10000000 2M | io mem (ARM9 / first 2MB)
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.word 0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)
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.word 0x1FF00027 @ 1FF00000 1M | dsp / axi wram
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.word 0x1800002D @ 18000000 8M | vram (+ 2MB)
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