forked from Mirror/GodMode9
556c75c337
* Fixed card reading (I didn't notice I broke it) * Fixed cart swapping * Still unsupported: CTR carts * Still hangs if cart has no SPI flash (see WarioWare DIY) The initialization code was simplified to only enable the SPICARD interface, which assumes the *TRCARD interface has been initialized beforehand. To keep things simple, I just wrapped SPIWriteRead with SPICARD_Init and SPICARD_deinit (which does the exact opposite)
121 lines
2.9 KiB
C
121 lines
2.9 KiB
C
/*
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* This file is part of fastboot 3DS
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* Copyright (C) 2019 derrek, profi200
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "types.h"
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#include "spicard.h"
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#include "delay.h"
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#define REG_CFG9_CARDCTL *((vu16*)0x1000000C)
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#define SPICARD_REGS_BASE 0x1000D800
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#define REG_NSPI_CNT *((vu32*)(SPICARD_REGS_BASE + 0x00))
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#define REG_NSPI_DONE *((vu32*)(SPICARD_REGS_BASE + 0x04))
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#define REG_NSPI_BLKLEN *((vu32*)(SPICARD_REGS_BASE + 0x08))
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#define REG_NSPI_FIFO *((vu32*)(SPICARD_REGS_BASE + 0x0C))
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#define REG_NSPI_STATUS *((vu32*)(SPICARD_REGS_BASE + 0x10))
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#define REG_NSPI_AUTOPOLL *((vu32*)(SPICARD_REGS_BASE + 0x14))
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#define REG_NSPI_INT_MASK *((vu32*)(SPICARD_REGS_BASE + 0x18))
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#define REG_NSPI_INT_STAT *((vu32*)(SPICARD_REGS_BASE + 0x1C))
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static inline void nspiWaitBusy(void)
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{
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while(REG_NSPI_CNT & NSPI_CNT_ENABLE);
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}
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static inline void nspiWaitFifoBusy(void)
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{
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while(REG_NSPI_STATUS & NSPI_STATUS_BUSY);
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}
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void SPICARD_init(void)
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{
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REG_CFG9_CARDCTL |= 1u<<8;
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}
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void SPICARD_deinit(void)
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{
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REG_CFG9_CARDCTL &= ~(1u<<8);
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}
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/*
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bool _SPICARD_autoPollBit(u32 params)
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{
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REG_NSPI_AUTOPOLL = NSPI_AUTOPOLL_START | params;
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u32 res;
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do
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{
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__wfi();
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res = REG_NSPI_INT_STAT;
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} while(!(res & (NSPI_INT_AP_TIMEOUT | NSPI_INT_AP_SUCCESS)));
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REG_NSPI_INT_STAT = res; // Aknowledge
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return (res & NSPI_INT_AP_TIMEOUT) == 0; // Timeout error
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}
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*/
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void SPICARD_writeRead(NspiClk clk, const void *in, void *out, u32 inSize, u32 outSize, bool done)
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{
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const u32 cntParams = NSPI_CNT_ENABLE | NSPI_CNT_BUS_1BIT | clk;
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REG_CFG9_CARDCTL |= 1u<<8;
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u32 buf;
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char *in_ = (char *) in;
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char *out_ = (char *) out;
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if(in_)
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{
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REG_NSPI_BLKLEN = inSize;
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REG_NSPI_CNT = cntParams | NSPI_CNT_DIRE_WRITE;
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u32 counter = 0;
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do
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{
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if((counter & 31) == 0) nspiWaitFifoBusy();
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memcpy(&buf, in_, min(4, inSize - counter));
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REG_NSPI_FIFO = buf;
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counter += 4;
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in_ += 4;
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} while(counter < inSize);
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nspiWaitBusy();
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}
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if(out_)
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{
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REG_NSPI_BLKLEN = outSize;
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REG_NSPI_CNT = cntParams | NSPI_CNT_DIRE_READ;
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u32 counter = 0;
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do
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{
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if((counter & 31) == 0) nspiWaitFifoBusy();
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buf = REG_NSPI_FIFO;
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memcpy(out_, &buf, min(4, outSize - counter));
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counter += 4;
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out_ += 4;
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} while(counter < outSize);
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nspiWaitBusy();
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}
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if(done) REG_NSPI_DONE = NSPI_DONE;
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}
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