forked from Mirror/GodMode9
refactored SPI and CODEC drivers, getting ready to move all SPI ops to the ARM11
This commit is contained in:
Wolfvak
d0k3
parent
1b04ca4fa1
commit
b52bf3b9a5
@ -25,32 +25,16 @@
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#define CPAD_FACTOR (150)
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/* SPI stuff */
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static void CODEC_DualTX(u8 *tx0, u8 len0, u8 *tx1, u8 len1)
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static void CODEC_WriteRead(u32 *txb, u8 txl, u32 *rxb, u8 rxl)
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{
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SPI_XferInfo xfers[2];
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xfers[0].buf = (u32*)tx0;
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xfers[0].len = len0;
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xfers[0].buf = txb;
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xfers[0].len = txl;
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xfers[0].read = false;
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xfers[1].buf = (u32*)tx1;
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xfers[1].len = len1;
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xfers[1].read = false;
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SPI_DoXfer(CODEC_SPI_DEV, xfers, 2);
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}
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static void CODEC_WriteRead(u8 *tx_buf, u8 tx_len,
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u8 *rx_buf, u8 rx_len)
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{
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SPI_XferInfo xfers[2];
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xfers[0].buf = (u32*)tx_buf;
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xfers[0].len = tx_len;
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xfers[0].read = false;
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xfers[1].buf = (u32*)rx_buf;
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xfers[1].len = rx_len;
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xfers[1].buf = rxb;
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xfers[1].len = rxl;
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xfers[1].read = true;
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SPI_DoXfer(CODEC_SPI_DEV, xfers, 2);
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@ -58,60 +42,49 @@ static void CODEC_WriteRead(u8 *tx_buf, u8 tx_len,
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static void CODEC_RegSelect(u8 reg)
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{
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u8 buffer1[4];
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u8 buffer2[0x40];
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SPI_XferInfo xfer;
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u32 cmd;
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buffer1[0] = 0;
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buffer2[0] = reg;
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cmd = reg << 8;
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CODEC_DualTX(buffer1, 1, buffer2, 1);
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xfer.buf = &cmd;
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xfer.len = 2;
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xfer.read = false;
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SPI_DoXfer(CODEC_SPI_DEV, &xfer, 1);
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}
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static u8 CODEC_RegRead(u8 offset)
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static u8 CODEC_RegRead(u8 reg)
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{
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u8 buffer_wr[8];
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u8 buffer_rd[0x40];
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buffer_wr[0] = 1 | (offset << 1);
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CODEC_WriteRead(buffer_wr, 1, buffer_rd, 1);
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return buffer_rd[0];
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u32 cmd, ret;
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cmd = (reg << 1) | 1;
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CODEC_WriteRead(&cmd, 1, &ret, 1);
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return ret;
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}
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static void CODEC_RegWrite(u8 reg, u8 val)
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{
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u8 buffer1[8];
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u8 buffer2[0x40];
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SPI_XferInfo xfer;
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u32 cmd;
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buffer1[0] = (reg << 1); // Write
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buffer2[0] = val;
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cmd = (val << 8) | (reg << 1);
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CODEC_DualTX(buffer1, 1, buffer2, 1);
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xfer.buf = &cmd;
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xfer.len = 2;
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xfer.read = false;
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SPI_DoXfer(CODEC_SPI_DEV, &xfer, 1);
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}
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static void CODEC_RegReadBuf(u8 offset, void *buffer, u8 size)
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static void CODEC_RegReadBuf(u8 reg, u32 *out, u8 size)
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{
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u8 buffer_wr[0x10];
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buffer_wr[0] = 1 | (offset << 1);
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CODEC_WriteRead(buffer_wr, 1, buffer, size);
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u32 cmd = (reg << 1) | 1;
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CODEC_WriteRead(&cmd, 1, out, size);
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}
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static void CODEC_RegMask(u8 offset, u8 mask0, u8 mask1)
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static void CODEC_RegMask(u8 reg, u8 mask0, u8 mask1)
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{
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u8 buffer1[4];
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u8 buffer2[0x40];
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buffer1[0] = 1 | (offset << 1);
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CODEC_WriteRead(buffer1, 1, buffer2, 1);
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buffer1[0] = offset << 1;
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buffer2[0] = (buffer2[0] & ~mask1) | (mask0 & mask1);
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CODEC_DualTX(buffer1, 1, buffer2, 1);
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CODEC_RegWrite(reg, (CODEC_RegRead(reg) & ~mask1) | (mask0 & mask1));
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}
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void CODEC_Init(void)
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@ -147,7 +120,7 @@ void CODEC_Init(void)
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CODEC_RegMask(0x25, 0x10, 0x3C);
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}
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static void CODEC_GetRawData(u8 *buffer)
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void CODEC_GetRawData(u32 *buffer)
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{
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CODEC_RegSelect(0x67);
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CODEC_RegRead(0x26);
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@ -157,11 +130,12 @@ static void CODEC_GetRawData(u8 *buffer)
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void CODEC_Get(CODEC_Input *input)
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{
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u8 raw_data[0x34];
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u32 raw_data_buf[0x34 / 4];
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u8 *raw_data = (u8*)raw_data_buf;
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s16 cpad_x, cpad_y;
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bool ts_pressed;
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CODEC_GetRawData(raw_data);
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CODEC_GetRawData(raw_data_buf);
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cpad_x = ((raw_data[0x24] << 8 | raw_data[0x25]) & 0xFFF) - 2048;
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cpad_y = ((raw_data[0x14] << 8 | raw_data[0x15]) & 0xFFF) - 2048;
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@ -9,4 +9,5 @@ typedef struct {
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void CODEC_Init(void);
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void CODEC_GetRawData(u32 *buffer);
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void CODEC_Get(CODEC_Input *input);
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@ -15,83 +15,73 @@
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#include "hw/spi.h"
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#define CFG_SPI_CNT ((vu32*)0x101401C0)
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#define REG_CFG_SPI_CNT ((vu16*)0x101401C0)
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// TODO: CURRENTLY HARDCODED FOR DEVICE 3 (TOUCHSCREEN)
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// IF ANY OTHER DEVICES ARE TO BE USED, ANOTHER BUS MUST
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// BE ACCESSED, CHECK 3dbrew.org/wiki/SPI_{Registers, Services}
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static const u32 SPI_Buses[] = { 0x10142800 };
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#define REG_SPI(b, n) (*(vu32*)(SPI_Buses[b] + (n)))
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#define REG_SPI(bus, reg) (*((vu32*)((bus) + (reg))))
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#define REG_SPI_CNT REG_SPI(0, 0x00)
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#define REG_SPI_DONE REG_SPI(0, 0x04)
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#define REG_SPI_BLKLEN REG_SPI(0, 0x08)
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#define REG_SPI_FIFO REG_SPI(0, 0x0C)
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#define REG_SPI_STATUS REG_SPI(0, 0x10)
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#define REG_SPI_BUS0 (0x10160800)
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#define REG_SPI_BUS1 (0x10142800)
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#define REG_SPI_BUS2 (0x10143800)
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#define SPI_CNT_BUSY BIT(15)
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#define SPI_CNT_START BIT(15)
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#define REG_SPI_CONTROL 0x00
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#define REG_SPI_DONE 0x04
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#define REG_SPI_BLKLEN 0x08
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#define REG_SPI_FIFO 0x0C
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#define REG_SPI_STAT 0x10
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#define SPI_CNT_READ (0)
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#define SPI_CNT_WRITE BIT(13)
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#define SPI_CNT_RATE(n) (n)
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#define SPI_CNT_CS(n) ((n) << 6)
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#define SPI_CONTROL_RATE(n) (n)
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#define SPI_CONTROL_CS(n) ((n) << 6)
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#define SPI_DIRECTION_READ (0)
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#define SPI_DIRECTION_WRITE BIT(13)
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#define SPI_CONTROL_BUSY BIT(15)
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#define SPI_CONTROL_START BIT(15)
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#define SPI_STAT_BUSY BIT(0)
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#define SPI_FIFO_WIDTH (32)
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static u8 SPI_GetDevSelect(u32 dev)
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static struct {
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u32 bus;
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u32 regcfg;
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} SPI_Devices[] = {
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{REG_SPI_BUS0, SPI_CONTROL_RATE(2) | SPI_CONTROL_CS(0)}, // device 0
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{REG_SPI_BUS0, SPI_CONTROL_RATE(0) | SPI_CONTROL_CS(1)},
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{REG_SPI_BUS0, SPI_CONTROL_RATE(0) | SPI_CONTROL_CS(2)},
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{REG_SPI_BUS1, SPI_CONTROL_RATE(5) | SPI_CONTROL_CS(0)},
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// TODO: complete this table
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};
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static void SPI_WaitBusy(u32 bus)
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{
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static const u8 SPI_DevSelect[] = { 0, 1, 2, 0, 1, 2 };
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if (dev < countof(SPI_DevSelect)) {
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return SPI_DevSelect[dev];
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} else {
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return 0;
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}
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while(REG_SPI(bus, REG_SPI_CONTROL) & SPI_CONTROL_BUSY);
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}
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static u8 SPI_GetDevBaudrate(u32 dev)
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static void SPI_WaitFIFO(u32 bus)
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{
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static const u8 SPI_BaudRates[] = { 2, 0, 0, 5 };
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if (dev < countof(SPI_BaudRates)) {
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return SPI_BaudRates[dev];
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} else {
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return 0;
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}
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while(REG_SPI(bus, REG_SPI_STAT) & SPI_STAT_BUSY);
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}
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static void SPI_WaitBusy(void)
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static void SPI_Done(u32 bus)
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{
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while(REG_SPI_CNT & SPI_CNT_BUSY);
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REG_SPI(bus, REG_SPI_DONE) = 0;
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}
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static void SPI_WaitFIFO(void)
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{
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while(REG_SPI_STATUS & SPI_STAT_BUSY);
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}
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static void SPI_Done(void)
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{
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REG_SPI_DONE = 0;
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}
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static void SPI_SingleXfer(u32 reg, bool read, u32 *buffer, u32 len)
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static void SPI_SingleXfer(u32 reg, u32 bus, u32 *buffer, u32 len, bool read)
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{
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u32 pos = 0;
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REG_SPI_BLKLEN = len;
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REG_SPI_CNT = reg | (read ? SPI_CNT_READ : SPI_CNT_WRITE) | SPI_CNT_START;
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REG_SPI(bus, REG_SPI_BLKLEN) = len;
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REG_SPI(bus, REG_SPI_CONTROL) = reg |
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(read ? SPI_DIRECTION_READ : SPI_DIRECTION_WRITE) | SPI_CONTROL_START;
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do {
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if ((pos % SPI_FIFO_WIDTH) == 0)
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SPI_WaitFIFO();
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SPI_WaitFIFO(bus);
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if (read) {
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buffer[pos / 4] = REG_SPI_FIFO;
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buffer[pos / 4] = REG_SPI(bus, REG_SPI_FIFO);
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} else {
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REG_SPI_FIFO = buffer[pos / 4];
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REG_SPI(bus, REG_SPI_FIFO) = buffer[pos / 4];
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}
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pos += 4;
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@ -100,30 +90,27 @@ static void SPI_SingleXfer(u32 reg, bool read, u32 *buffer, u32 len)
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int SPI_DoXfer(u32 dev, SPI_XferInfo *xfers, u32 xfer_cnt)
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{
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u32 dev_cfg;
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int baud, cs;
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u32 bus;
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u32 dev_reg;
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baud = SPI_GetDevBaudrate(dev);
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cs = SPI_GetDevSelect(dev);
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dev_cfg = SPI_CNT_RATE(baud) | SPI_CNT_CS(cs);
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bus = SPI_Devices[dev].bus;
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dev_reg = SPI_Devices[dev].regcfg;
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for (u32 i = 0; i < xfer_cnt; i++) {
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SPI_XferInfo *xfer = &xfers[i];
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SPI_WaitBusy();
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SPI_SingleXfer(dev_cfg, xfer->read, xfer->buf, xfer->len);
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SPI_WaitBusy(bus);
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SPI_SingleXfer(dev_reg, bus, xfer->buf, xfer->len, xfer->read);
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}
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SPI_WaitBusy();
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SPI_Done();
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SPI_WaitBusy(bus);
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SPI_Done(bus);
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return 0;
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}
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void SPI_Init(void)
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{
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// Hack: here all registers should be set to the "new" mode
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// but GM9 uses the old interface to access NVRAM
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// as such, only the bus used by CODEC will be set to new
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// *CFG_SPI_CNT = 7;
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*CFG_SPI_CNT = BIT(1);
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// This cuts off access from the old SPI
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// interface used during the NDS days
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*REG_CFG_SPI_CNT = 7;
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}
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