Refactored screeninit

This commit is contained in:
Wolfvak 2017-08-21 21:01:18 -03:00 committed by d0k3
parent b333380bc0
commit 5104deff9e
10 changed files with 363 additions and 198 deletions

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@ -15,57 +15,63 @@
#endif #endif
enum { enum {
PXI_NOCMD = 0, PXI_NONE = 0,
PXI_SETBRIGHTNESS = 1 PXI_READY,
PXI_BUSY,
PXI_BRIGHTNESS
}; };
#define PXI_SYNC_RECV ((volatile uint8_t*)(PXI_BASE + 0x00)) #define PXI_MAXBUFLEN (2048)
#define PXI_SYNC_SEND ((volatile uint8_t*)(PXI_BASE + 0x01)) #define PXI_FIFO_LEN (16)
#define PXI_SYNC_IRQ ((volatile uint8_t*)(PXI_BASE + 0x03))
#define PXI_CNT ((volatile uint16_t*)(PXI_BASE + 0x04))
#define PXI_SEND ((volatile uint32_t*)(PXI_BASE + 0x08))
#define PXI_RECV ((volatile uint32_t*)(PXI_BASE + 0x0C))
#define PXI_CNT_SEND_FIFO_EMPTY (1<<0) #define PXI_SYNC_RECV ((vu8*)(PXI_BASE + 0x00))
#define PXI_CNT_SEND_FIFO_FULL (1<<1) #define PXI_SYNC_SEND ((vu8*)(PXI_BASE + 0x01))
#define PXI_CNT_SEND_FIFO_EMPTY_IRQ (1<<2) #define PXI_SYNC_IRQ ((vu8*)(PXI_BASE + 0x03))
#define PXI_CNT_SEND_FIFO_FLUSH (1<<3) #define PXI_SYNC ((vu32*)(PXI_BASE + 0x00))
#define PXI_CNT_RECV_FIFO_EMPTY (1<<8) #define PXI_CNT ((vu16*)(PXI_BASE + 0x04))
#define PXI_CNT_RECV_FIFO_FULL (1<<9) #define PXI_SEND ((vu32*)(PXI_BASE + 0x08))
#define PXI_CNT_RECV_FIFO_NEMPTY_IRQ (1<<10) #define PXI_RECV ((vu32*)(PXI_BASE + 0x0C))
#define PXI_CNT_ERROR_ACK (1<<14)
#define PXI_CNT_ENABLE_FIFO (1<<15)
#define PXI_SYNC_TRIGGER_MPCORE (1<<5) #define PXI_CNT_SEND_FIFO_EMPTY (BIT(0))
#define PXI_SYNC_TRIGGER_OLDARM (1<<6) #define PXI_CNT_SEND_FIFO_FULL (BIT(1))
#define PXI_SYNC_ENABLE_IRQ (1<<7) #define PXI_CNT_SEND_FIFO_EMPTY_IRQ (BIT(2))
#define PXI_CNT_SEND_FIFO_FLUSH (BIT(3))
#define PXI_CNT_RECV_FIFO_EMPTY (BIT(8))
#define PXI_CNT_RECV_FIFO_FULL (BIT(9))
#define PXI_CNT_RECV_FIFO_NEMPTY_IRQ (BIT(10))
#define PXI_CNT_ERROR_ACK (BIT(14))
#define PXI_CNT_ENABLE_FIFO (BIT(15))
static inline void PXI_SetRemote(u8 msg) #define PXI_SYNC_TRIGGER_MPCORE (BIT(5))
#define PXI_SYNC_TRIGGER_OLDARM (BIT(6))
#define PXI_SYNC_ENABLE_IRQ (BIT(7))
void PXI_SetRemote(u8 msg)
{ {
*PXI_SYNC_SEND = msg; *PXI_SYNC_SEND = msg;
} }
static inline u8 PXI_GetRemote(void) u8 PXI_GetRemote(void)
{ {
return *PXI_SYNC_RECV; return *PXI_SYNC_RECV;
} }
static inline void PXI_EnableIRQ(void) void PXI_WaitRemote(u8 msg)
{
while(*PXI_SYNC_RECV != msg);
}
void PXI_EnableIRQ(void)
{ {
*PXI_SYNC_IRQ = PXI_SYNC_ENABLE_IRQ; *PXI_SYNC_IRQ = PXI_SYNC_ENABLE_IRQ;
} }
static inline void PXI_DisableIRQ(void) void PXI_DisableIRQ(void)
{ {
*PXI_SYNC_IRQ = 0; *PXI_SYNC_IRQ = 0;
} }
static inline void PXI_Wait(void) void PXI_Sync(void)
{
while(PXI_GetRemote() != PXI_NOCMD);
}
static inline void PXI_Sync(void)
{ {
#ifdef ARM9 #ifdef ARM9
*PXI_SYNC_IRQ |= PXI_SYNC_TRIGGER_MPCORE; *PXI_SYNC_IRQ |= PXI_SYNC_TRIGGER_MPCORE;
@ -74,14 +80,19 @@ static inline void PXI_Sync(void)
#endif #endif
} }
static inline void PXI_Reset(void) void PXI_Reset(void)
{ {
*PXI_SYNC_SEND = 0; *PXI_SYNC = 0;
*PXI_SYNC_IRQ = 0; *PXI_CNT = PXI_CNT_SEND_FIFO_FLUSH;
*PXI_CNT = PXI_CNT_SEND_FIFO_FLUSH | PXI_CNT_ENABLE_FIFO; for (int i=0; i<16; i++) {
*PXI_RECV;
}
*PXI_CNT = 0;
*PXI_CNT = PXI_CNT_ENABLE_FIFO;
return;
} }
static inline void PXI_Send(u32 w) void PXI_Send(u32 w)
{ {
while(*PXI_CNT & PXI_CNT_SEND_FIFO_FULL); while(*PXI_CNT & PXI_CNT_SEND_FIFO_FULL);
do { do {
@ -90,7 +101,7 @@ static inline void PXI_Send(u32 w)
return; return;
} }
static inline u32 PXI_Recv(void) u32 PXI_Recv(void)
{ {
u32 ret; u32 ret;
while(*PXI_CNT & PXI_CNT_RECV_FIFO_EMPTY); while(*PXI_CNT & PXI_CNT_RECV_FIFO_EMPTY);
@ -99,3 +110,31 @@ static inline u32 PXI_Recv(void)
} while(*PXI_CNT & PXI_CNT_ERROR_ACK); } while(*PXI_CNT & PXI_CNT_ERROR_ACK);
return ret; return ret;
} }
void PXI_SendArray(const u32 *w, u32 c)
{
if (c>PXI_FIFO_LEN) c=PXI_FIFO_LEN;
for (u32 i=0; i<c; i++) {
PXI_Send(w[i]);
}
return;
}
void PXI_RecvArray(u32 *w, u32 c)
{
if (c>PXI_FIFO_LEN) c=PXI_FIFO_LEN;
for (u32 i=0; i<c; i++) {
w[i] = PXI_Recv();
}
return;
}
void PXI_DoCMD(u8 cmd, u32 *args, u32 argc)
{
PXI_WaitRemote(PXI_READY);
PXI_SendArray(args, argc);
PXI_SetRemote(cmd);
PXI_Sync();
PXI_WaitRemote(PXI_READY);
return;
}

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@ -17,6 +17,7 @@ INCLUDE := -I$(dir_source) -I../common
ASFLAGS := $(ARCH) -x assembler-with-cpp $(INCLUDE) ASFLAGS := $(ARCH) -x assembler-with-cpp $(INCLUDE)
CFLAGS := $(ARCH) -Wall -Wextra -MMD -MP -fno-builtin \ CFLAGS := $(ARCH) -Wall -Wextra -MMD -MP -fno-builtin \
-Wno-unused-function -Wno-unused-variable \
-std=c11 -O2 -flto -ffast-math -Wno-main $(INCLUDE) -std=c11 -O2 -flto -ffast-math -Wno-main $(INCLUDE)
LDFLAGS := -nostdlib -nostartfiles LDFLAGS := -nostdlib -nostartfiles

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@ -1,16 +1,12 @@
@ This file was kindly provided by Wolfvak - thank you!
.section .text.boot .section .text.boot
.arm .align 4
#include <arm.h> #include <arm.h>
.global __boot .global __boot
__boot: __boot:
@ Disable interrupts and switch to IRQ cpsid aif, #(SR_SVC_MODE)
cpsid if, #(SR_SVC_MODE)
@ Writeback and invalidate caches
mov r0, #0 mov r0, #0
mcr p15, 0, r0, c7, c7, 0 mcr p15, 0, r0, c7, c7, 0
mcr p15, 0, r0, c7, c14, 0 mcr p15, 0, r0, c7, c14, 0
@ -23,7 +19,6 @@ __boot:
ldr r1, =0x0000000F ldr r1, =0x0000000F
ldr r2, =0x00000000 ldr r2, =0x00000000
@ MMU disabled, Caches disabled, other misc crap going on
mcr p15, 0, r0, c1, c0, 0 mcr p15, 0, r0, c1, c0, 0
mcr p15, 0, r1, c1, c0, 1 mcr p15, 0, r1, c1, c0, 1
mcr p15, 0, r2, c1, c0, 2 mcr p15, 0, r2, c1, c0, 2
@ -37,5 +32,4 @@ __boot:
blt .Lclearbss blt .Lclearbss
bl main bl main
b __boot b __boot

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@ -1,13 +1,8 @@
/*
Written by Wolfvak, specially sublicensed under the GPLv2
Read LICENSE for more details
*/
#include <types.h> #include <types.h>
#include <cpu.h> #include <cpu.h>
#include <gic.h> #include <gic.h>
#define IRQ_BASE ((vu32*)0x1FFFFFA0) #define IRQVECTOR_BASE ((vu32*)0x1FFFFFA0)
irq_handler handler_table[MAX_IRQ]; irq_handler handler_table[MAX_IRQ];
extern void (*main_irq_handler)(void); extern void (*main_irq_handler)(void);
@ -54,7 +49,7 @@ void GIC_Reset(void)
} }
} }
IRQ_BASE[1] = (u32)&main_irq_handler; IRQVECTOR_BASE[1] = (u32)&main_irq_handler;
IRQ_BASE[0] = 0xE51FF004; IRQVECTOR_BASE[0] = 0xE51FF004;
return; return;
} }

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@ -1,8 +1,3 @@
/*
Written by Wolfvak, specially sublicensed under the GPLv2
Read LICENSE for more details
*/
#pragma once #pragma once
#include <types.h> #include <types.h>

184
screeninit/source/gpulcd.c Normal file
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@ -0,0 +1,184 @@
#include <vram.h>
#include <gpulcd.h>
#include <types.h>
void LCD_SetBrightness(u32 screen, u32 brightness)
{
vu32 *lcd_reg;
if (screen & 1) {
lcd_reg = LCD_CFG(0xA40);
} else {
lcd_reg = LCD_CFG(0x240);
}
*lcd_reg = brightness & 0xFF;
return;
}
void LCD_Initialize(u32 brightness)
{
brightness &= 0xFF;
*LCD_CFG(0x014) = 0x00000001;
*LCD_CFG(0x00C) &= 0xFFFEFFFE;
*LCD_CFG(0x240) = brightness;
*LCD_CFG(0xA40) = brightness;
*LCD_CFG(0x244) = 0x1023E;
*LCD_CFG(0xA44) = 0x1023E;
}
void LCD_Deinitialize(void)
{
*LCD_CFG(0x244) = 0;
*LCD_CFG(0xA44) = 0;
*LCD_CFG(0x00C) = 0;
*LCD_CFG(0x014) = 0;
return;
}
void GPU_PSCFill(u32 start, u32 end, u32 fv)
{
u32 mp;
if (start > end) {
return;
}
start = GPU_ADDR(start);
end = GPU_ADDR(end);
mp = (start+end)/2;
*GPU_PSC0(PSC_SADDR) = start;
*GPU_PSC0(PSC_EADDR) = mp;
*GPU_PSC0(PSC_FILL) = fv;
*GPU_PSC1(PSC_SADDR) = mp;
*GPU_PSC1(PSC_EADDR) = end;
*GPU_PSC1(PSC_FILL) = fv;
*GPU_PSC0(PSC_CNT) = PSC_START | PSC_32BIT;
*GPU_PSC1(PSC_CNT) = PSC_START | PSC_32BIT;
while(!((*GPU_PSC0(PSC_CNT) & PSC_DONE) && (*GPU_PSC1(PSC_CNT) & PSC_DONE)));
return;
}
void GPU_SetFramebuffers(const u32 *framebuffers)
{
*GPU_PDC0(0x68) = framebuffers[0];
*GPU_PDC0(0x6C) = framebuffers[1];
*GPU_PDC0(0x94) = framebuffers[2];
*GPU_PDC0(0x98) = framebuffers[3];
*GPU_PDC1(0x68) = framebuffers[4];
*GPU_PDC1(0x6C) = framebuffers[5];
*GPU_PDC0(0x78) = 0;
*GPU_PDC1(0x78) = 0;
return;
}
void GPU_SetFramebufferMode(u32 screen, u32 mode)
{
u32 stride, cfg;
vu32 *fbcfg_reg, *fbstr_reg;
mode &= 7;
screen &= 1;
cfg = PDC_FIXSTRIP | mode;
if (screen) {
fbcfg_reg = GPU_PDC1(0x70);
fbstr_reg = GPU_PDC1(0x90);
} else {
fbcfg_reg = GPU_PDC0(0x70);
fbstr_reg = GPU_PDC0(0x90);
cfg |= PDC_MAINSCREEN;
}
switch(mode) {
case PDC_RGBA8:
stride = 960;
break;
case PDC_RGB24:
stride = 720;
break;
default:
stride = 480;
break;
}
*fbcfg_reg = cfg;
*fbstr_reg = stride;
return;
}
void GPU_Init(void)
{
LCD_Initialize(0x20);
if (*GPU_CNT != 0x1007F) {
*GPU_CNT = 0x1007F;
*GPU_PDC0(0x00) = 0x000001C2;
*GPU_PDC0(0x04) = 0x000000D1;
*GPU_PDC0(0x08) = 0x000001C1;
*GPU_PDC0(0x0C) = 0x000001C1;
*GPU_PDC0(0x10) = 0x00000000;
*GPU_PDC0(0x14) = 0x000000CF;
*GPU_PDC0(0x18) = 0x000000D1;
*GPU_PDC0(0x1C) = 0x01C501C1;
*GPU_PDC0(0x20) = 0x00010000;
*GPU_PDC0(0x24) = 0x0000019D;
*GPU_PDC0(0x28) = 0x00000002;
*GPU_PDC0(0x2C) = 0x00000192;
*GPU_PDC0(0x30) = 0x00000192;
*GPU_PDC0(0x34) = 0x00000192;
*GPU_PDC0(0x38) = 0x00000001;
*GPU_PDC0(0x3C) = 0x00000002;
*GPU_PDC0(0x40) = 0x01960192;
*GPU_PDC0(0x44) = 0x00000000;
*GPU_PDC0(0x48) = 0x00000000;
*GPU_PDC0(0x5C) = 0x00F00190;
*GPU_PDC0(0x60) = 0x01C100D1;
*GPU_PDC0(0x64) = 0x01920002;
*GPU_PDC0(0x68) = VRAM_START;
*GPU_PDC0(0x6C) = VRAM_START;
*GPU_PDC0(0x70) = 0x00080340;
*GPU_PDC0(0x74) = 0x00010501;
*GPU_PDC0(0x90) = 0x000003C0;
*GPU_PDC0(0x94) = VRAM_START;
*GPU_PDC0(0x98) = VRAM_START;
*GPU_PDC0(0x9C) = 0x00000000;
for (u32 i=0; i<256; i++)
*GPU_PDC0(0x84) = 0x10101 * i;
*GPU_PDC1(0x00) = 0x000001C2;
*GPU_PDC1(0x04) = 0x000000D1;
*GPU_PDC1(0x08) = 0x000001C1;
*GPU_PDC1(0x0C) = 0x000001C1;
*GPU_PDC1(0x10) = 0x000000CD;
*GPU_PDC1(0x14) = 0x000000CF;
*GPU_PDC1(0x18) = 0x000000D1;
*GPU_PDC1(0x1C) = 0x01C501C1;
*GPU_PDC1(0x20) = 0x00010000;
*GPU_PDC1(0x24) = 0x0000019D;
*GPU_PDC1(0x28) = 0x00000052;
*GPU_PDC1(0x2C) = 0x00000192;
*GPU_PDC1(0x30) = 0x00000192;
*GPU_PDC1(0x34) = 0x0000004F;
*GPU_PDC1(0x38) = 0x00000050;
*GPU_PDC1(0x3C) = 0x00000052;
*GPU_PDC1(0x40) = 0x01980194;
*GPU_PDC1(0x44) = 0x00000000;
*GPU_PDC1(0x48) = 0x00000011;
*GPU_PDC1(0x5C) = 0x00F00140;
*GPU_PDC1(0x60) = 0x01C100d1;
*GPU_PDC1(0x64) = 0x01920052;
*GPU_PDC1(0x68) = VRAM_START;
*GPU_PDC1(0x6C) = VRAM_START;
*GPU_PDC1(0x70) = 0x00080300;
*GPU_PDC1(0x74) = 0x00010501;
*GPU_PDC1(0x90) = 0x000003C0;
*GPU_PDC1(0x9C) = 0x00000000;
for (u32 i=0; i<256; i++)
*GPU_PDC1(0x84) = 0x10101 * i;
}
return;
}

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@ -0,0 +1,47 @@
#pragma once
#include <types.h>
#define GPU_ADDR(x) ((x)>>3)
#define GPU_BOX(w,h) ((w) | (h)<<16)
#define GPU_CNT ((vu32*)(0x10141200))
#define LCD_CFG(x) ((vu32*)(0x10202000 + (x)))
void LCD_SetBrightness(u32 screen, u32 brightness);
void LCD_Deinitialize(void);
#define GPU_PSC0(x) ((vu32*)(0x10400010 + (x)))
#define GPU_PSC1(x) ((vu32*)(0x10400020 + (x)))
#define PSC_SADDR (0x00)
#define PSC_EADDR (0x04)
#define PSC_FILL (0x08)
#define PSC_CNT (0x0C)
#define PSC_START (BIT(0))
#define PSC_DONE (BIT(1))
#define PSC_32BIT (2<<8)
#define PSC_24BIT (1<<8)
#define PSC_16BIT (0<<8)
void GPU_PSCWait(void);
void GPU_PSCFill(u32 start, u32 end, u32 fv);
#define GPU_PDC0(x) ((vu32*)(0x10400400 + (x)))
#define GPU_PDC1(x) ((vu32*)(0x10400500 + (x)))
#define PDC_RGBA8 (0<<0)
#define PDC_RGB24 (1<<0)
#define PDC_RGB565 (2<<0)
#define PDC_RGB5A1 (3<<0)
#define PDC_RGBA4 (4<<0)
#define PDC_PARALLAX (BIT(5))
#define PDC_MAINSCREEN (BIT(6))
#define PDC_FIXSTRIP (BIT(7))
void GPU_SetFramebuffers(const u32 *framebuffers);
void GPU_SetFramebufferMode(u32 screen, u32 mode);
void GPU_Init();

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@ -1,163 +1,77 @@
// screeninit source taken over from https://github.com/AuroraWright/arm9loaderhax/tree/master/payload_stage2/arm11
// check there for license info
// thanks go to AuroraWright
#include <types.h>
#include <arm.h>
#include <cpu.h> #include <cpu.h>
#include <gic.h>
#include <pxi.h> #include <pxi.h>
#include <gic.h>
#include <gpulcd.h>
#include <vram.h> #include <vram.h>
#include <types.h>
// see: https://github.com/AuroraWright/Luma3DS/blob/53209b9be0c264af00fb81b32146d27f0d9498ac/source/screen.h#L32-L34 vu32 *entrypoint = (vu32*)0x1FFFFFFC;
#define PDN_GPU_CNT (*(vu8 *)0x10141200)
#define ARESCREENSINITIALIZED (PDN_GPU_CNT != 1)
#define BASE_BRIGHTNESS (0x1F) void PXI_IRQHandler(void)
void screen_init(void)
{ {
char do_disco = !ARESCREENSINITIALIZED; char pxi_buf[PXI_MAXBUFLEN] = {0};
u32 pxi_args[PXI_FIFO_LEN] = {0};
u8 pxi_cmd;
*(vu32 *)0x10141200 = 0x1007F; pxi_cmd = PXI_GetRemote();
*(vu32 *)0x10202014 = 0x00000001; switch (pxi_cmd) {
*(vu32 *)0x1020200C &= 0xFFFEFFFE; default:
*(vu32 *)0x10202240 = BASE_BRIGHTNESS;
*(vu32 *)0x10202A40 = BASE_BRIGHTNESS;
*(vu32 *)0x10202244 = 0x1023E;
*(vu32 *)0x10202A44 = 0x1023E;
//Top screen
*(vu32 *)0x10400400 = 0x000001c2;
*(vu32 *)0x10400404 = 0x000000d1;
*(vu32 *)0x10400408 = 0x000001c1;
*(vu32 *)0x1040040c = 0x000001c1;
*(vu32 *)0x10400410 = 0x00000000;
*(vu32 *)0x10400414 = 0x000000cf;
*(vu32 *)0x10400418 = 0x000000d1;
*(vu32 *)0x1040041c = 0x01c501c1;
*(vu32 *)0x10400420 = 0x00010000;
*(vu32 *)0x10400424 = 0x0000019d;
*(vu32 *)0x10400428 = 0x00000002;
*(vu32 *)0x1040042c = 0x00000192;
*(vu32 *)0x10400430 = 0x00000192;
*(vu32 *)0x10400434 = 0x00000192;
*(vu32 *)0x10400438 = 0x00000001;
*(vu32 *)0x1040043c = 0x00000002;
*(vu32 *)0x10400440 = 0x01960192;
*(vu32 *)0x10400444 = 0x00000000;
*(vu32 *)0x10400448 = 0x00000000;
*(vu32 *)0x1040045C = 0x00f00190;
*(vu32 *)0x10400460 = 0x01c100d1;
*(vu32 *)0x10400464 = 0x01920002;
*(vu32 *)0x10400468 = VRAM_TOP_LA;
*(vu32 *)0x1040046C = VRAM_TOP_LB;
*(vu32 *)0x10400470 = 0x80341;
*(vu32 *)0x10400474 = 0x00010501;
*(vu32 *)0x10400478 = 0;
*(vu32 *)0x10400490 = 0x000002D0;
*(vu32 *)0x10400494 = VRAM_TOP_RA;
*(vu32 *)0x10400498 = VRAM_TOP_RB;
*(vu32 *)0x1040049C = 0x00000000;
//Bottom screen
*(vu32 *)0x10400500 = 0x000001c2;
*(vu32 *)0x10400504 = 0x000000d1;
*(vu32 *)0x10400508 = 0x000001c1;
*(vu32 *)0x1040050c = 0x000001c1;
*(vu32 *)0x10400510 = 0x000000cd;
*(vu32 *)0x10400514 = 0x000000cf;
*(vu32 *)0x10400518 = 0x000000d1;
*(vu32 *)0x1040051c = 0x01c501c1;
*(vu32 *)0x10400520 = 0x00010000;
*(vu32 *)0x10400524 = 0x0000019d;
*(vu32 *)0x10400528 = 0x00000052;
*(vu32 *)0x1040052c = 0x00000192;
*(vu32 *)0x10400530 = 0x00000192;
*(vu32 *)0x10400534 = 0x0000004f;
*(vu32 *)0x10400538 = 0x00000050;
*(vu32 *)0x1040053c = 0x00000052;
*(vu32 *)0x10400540 = 0x01980194;
*(vu32 *)0x10400544 = 0x00000000;
*(vu32 *)0x10400548 = 0x00000011;
*(vu32 *)0x1040055C = 0x00f00140;
*(vu32 *)0x10400560 = 0x01c100d1;
*(vu32 *)0x10400564 = 0x01920052;
*(vu32 *)0x10400568 = VRAM_BOT_A;
*(vu32 *)0x1040056C = VRAM_BOT_B;
*(vu32 *)0x10400570 = 0x80301;
*(vu32 *)0x10400574 = 0x00010501;
*(vu32 *)0x10400578 = 0;
*(vu32 *)0x10400590 = 0x000002D0;
*(vu32 *)0x1040059C = 0x00000000;
if (do_disco) {
for(u32 i = 0; i < 256; i++) {
*(vu32 *)0x10400484 = 0x10101 * i;
*(vu32 *)0x10400584 = 0x10101 * i;
}
}
vu32 *REGs_PSC0 = (vu32 *)0x10400010,
*REGs_PSC1 = (vu32 *)0x10400020;
REGs_PSC0[0] = VRAM_START >> 3;
REGs_PSC0[1] = ((VRAM_START + VRAM_END) / 2) >> 3;
REGs_PSC0[2] = 0;
REGs_PSC0[3] = (2 << 8) | 1;
REGs_PSC1[0] = ((VRAM_START + VRAM_END) / 2) >> 3;
REGs_PSC1[1] = VRAM_END >> 3;
REGs_PSC1[2] = 0;
REGs_PSC1[3] = (2 << 8) | 1;
while(!((REGs_PSC0[3] & 2) && (REGs_PSC1[3] & 2)));
return;
}
void set_brightness(u8 brightness)
{
*(vu32 *)0x10202240 = brightness;
*(vu32 *)0x10202A40 = brightness;
}
void pxi_interrupt_handler(void)
{
u8 msg = PXI_GetRemote();
switch(msg) {
case PXI_NOCMD:
break; break;
case PXI_SETBRIGHTNESS:
set_brightness(PXI_Recv()); case PXI_BRIGHTNESS:
{
PXI_RecvArray(pxi_args, 1);
PXI_SetRemote(PXI_BUSY);
LCD_SetBrightness(0, pxi_args[0]);
LCD_SetBrightness(1, pxi_args[0]);
break; break;
} }
PXI_SetRemote(PXI_NOCMD);
/* New CMD template:
case CMD_ID:
{
<var declarations/assignments>
<receive args from PXI FIFO>
<if necessary, copy stuff to pxi_buf>
PXI_SetRemote(PXI_BUSY);
<execute the command>
break;
}
*/
}
PXI_SetRemote(PXI_READY);
return; return;
} }
void main(void) void main(void)
{ {
vu32 *arm11Entry = (vu32 *)0x1FFFFFFC; u32 entry=0;
u32 entry;
PXI_Reset(); PXI_Reset();
GIC_Reset();
GIC_SetIRQ(IRQ_PXI_SYNC, pxi_interrupt_handler);
screen_init();
GPU_Init();
GPU_PSCFill(VRAM_START, VRAM_END, 0);
GPU_SetFramebuffers((u32[]){VRAM_TOP_LA, VRAM_TOP_LB,
VRAM_TOP_RA, VRAM_TOP_RB,
VRAM_BOT_A, VRAM_BOT_B});
GPU_SetFramebufferMode(0, PDC_RGB24);
GPU_SetFramebufferMode(1, PDC_RGB24);
GIC_Reset();
GIC_SetIRQ(IRQ_PXI_SYNC, PXI_IRQHandler);
PXI_EnableIRQ(); PXI_EnableIRQ();
CPU_EnableIRQ(); CPU_EnableIRQ();
// Clear ARM11 entrypoint PXI_SetRemote(PXI_READY);
*arm11Entry = 0;
// Wait for the entrypoint to be set, then branch to it *entrypoint = 0;
while((entry=*arm11Entry) == 0); while((entry=*entrypoint) == 0);
CPU_DisableIRQ(); CPU_DisableIRQ();
PXI_DisableIRQ(); PXI_DisableIRQ();
PXI_Reset(); PXI_Reset();
GIC_Reset(); GIC_Reset();
((void (*)())(entry))(); ((void (*)())(entry))();
} }

View File

@ -9,12 +9,10 @@ static int prev_brightness = -1;
void CheckBrightness() { void CheckBrightness() {
u8 curSlider; u8 curSlider;
I2C_readRegBuf(I2C_DEV_MCU, 0x09, &curSlider, 1); I2C_readRegBuf(I2C_DEV_MCU, 0x09, &curSlider, 1);
// Volume Slider value is always between 0x00 and 0x3F
curSlider >>= 2; curSlider >>= 2;
if (curSlider != prev_brightness) { if (curSlider != prev_brightness) {
PXI_Wait(); PXI_DoCMD(PXI_BRIGHTNESS, (u32[]){br_settings[curSlider]}, 1);
PXI_Send(br_settings[curSlider]);
PXI_SetRemote(PXI_SETBRIGHTNESS);
PXI_Sync();
prev_brightness = curSlider; prev_brightness = curSlider;
} }
return; return;
@ -22,7 +20,6 @@ void CheckBrightness() {
void ScreenOn() { void ScreenOn() {
wait_msec(3); // wait 3ms (cause profi200 said so) wait_msec(3); // wait 3ms (cause profi200 said so)
flushDCacheRange((u8*)0x23FFFE00, sizeof(u8*)*3); // this assumes CakeHax framebuffers, see ui.h
I2C_writeReg(I2C_DEV_MCU, 0x22, 0x2A); // poweron LCD I2C_writeReg(I2C_DEV_MCU, 0x22, 0x2A); // poweron LCD
} }

View File

@ -1,6 +1,5 @@
#include "godmode.h" #include "godmode.h"
#include "power.h" #include "power.h"
#include "pxi.h"
void main(int argc, char** argv) void main(int argc, char** argv)
{ {