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This commit is contained in:
d0k3 2016-04-12 12:35:59 +02:00
parent 018f0fd65c
commit 1750428342
1 changed files with 28 additions and 28 deletions
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56
source/abstraction/gw-start.s
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@ -6,36 +6,36 @@
.arm .arm
_vectors: _vectors:
ldr pc, =InfiniteLoop ldr pc, =InfiniteLoop
.pool .pool
ldr pc, =InfiniteLoop ldr pc, =InfiniteLoop
.pool .pool
ldr pc, =InfiniteLoop ldr pc, =InfiniteLoop
.pool .pool
ldr pc, =InfiniteLoop ldr pc, =InfiniteLoop
.pool .pool
ldr pc, =InfiniteLoop ldr pc, =InfiniteLoop
.pool .pool
ldr pc, =InfiniteLoop ldr pc, =InfiniteLoop
.pool .pool
_start: _start:
ldr sp,=0x22140000 ldr sp,=0x22140000
@@wait for the arm11 kernel threads to be ready @@wait for the arm11 kernel threads to be ready
ldr r1, =0x10000 ldr r1, =0x10000
waitLoop9: waitLoop9:
sub r1, #1 sub r1, #1
cmp r1, #0 cmp r1, #0
bgt waitLoop9 bgt waitLoop9
ldr r1, =0x10000 ldr r1, =0x10000
waitLoop92: waitLoop92:
sub r1, #1 sub r1, #1
cmp r1, #0 cmp r1, #0
bgt waitLoop92 bgt waitLoop92
@ Enable caches @ Enable caches
mrc p15, 0, r4, c1, c0, 0 @ read control register mrc p15, 0, r4, c1, c0, 0 @ read control register
@ -45,12 +45,12 @@ _start:
orr r4, r4, #(1<<0) @ - mpu enable orr r4, r4, #(1<<0) @ - mpu enable
mcr p15, 0, r4, c1, c0, 0 @ write control register mcr p15, 0, r4, c1, c0, 0 @ write control register
ldr sp,=0x22160000 ldr sp,=0x22160000
ldr r3, =main ldr r3, =main
blx r3 blx r3
.pool .pool
InfiniteLoop: InfiniteLoop:
b InfiniteLoop b InfiniteLoop
#endif // EXEC_GATEWAY #endif // EXEC_GATEWAY