forked from Mirror/GodMode9
57 lines
1.5 KiB
C
57 lines
1.5 KiB
C
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/*
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Written by Wolfvak, specially sublicensed under the GPLv2
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Read LICENSE for more details
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*/
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#pragma once
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#include <types.h>
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typedef void (*irq_handler)(u32);
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#define MAX_IRQ (0x80)
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#define GIC_BASE (0x17E00100)
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#define DIC_BASE (0x17E01000)
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/* Setting bit 0 enables the GIC */
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#define GIC_CONTROL ((vu32*)(GIC_BASE + 0x00))
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/* Bits [7:0] control the min priority accepted */
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#define GIC_PRIOMASK ((vu32*)(GIC_BASE + 0x04))
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/* When an IRQ occurrs, this register holds the IRQ ID */
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#define GIC_IRQACK ((vu32*)(GIC_BASE + 0x0C))
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/* Write the IRQ ID here to acknowledge it */
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#define GIC_IRQEND ((vu32*)(GIC_BASE + 0x10))
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/* Setting bit 0 enables the DIC */
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#define DIC_CONTROL ((vu32*)(DIC_BASE + 0x000))
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/*
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Write here to enable an IRQ ID
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The register address is DIC_SETENABLE + (N/32)*4 and its
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corresponding bit index is (N%32)
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*/
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#define DIC_SETENABLE ((vu32*)(DIC_BASE + 0x100))
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/* same as above but disables the IRQ */
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#define DIC_CLRENABLE ((vu32*)(DIC_BASE + 0x180))
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/* sets the IRQ priority */
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#define DIC_PRIORITY ((vu32*)(DIC_BASE + 0x400))
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/* specifies which CPUs are allowed to be forwarded the IRQ */
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#define DIC_PROCTGT ((vu8*)(DIC_BASE + 0x800))
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/*
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each irq has 2 bits assigned
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bit 0 = 0: uses 1-N model
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1: uses N-N model
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bit 1 = 0: level high active
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1: rising edge sensitive
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*/
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#define DIC_CFGREG ((vu32*)(DIC_BASE + 0xC00))
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void gic_irq_handler(void);
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void GIC_Configure(u32 irq_id, irq_handler hndl);
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void GIC_Reset(void);
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