2017-08-08 23:04:17 -03:00
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#pragma once
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/* Status Register flags */
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#define SR_USR_MODE (0x10)
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#define SR_FIQ_MODE (0x11)
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#define SR_IRQ_MODE (0x12)
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#define SR_SVC_MODE (0x13)
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#define SR_ABT_MODE (0x17)
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#define SR_UND_MODE (0x1B)
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#define SR_SYS_MODE (0x1F)
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#define SR_PMODE_MASK (0x1F)
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2017-08-12 16:04:20 -03:00
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#define SR_THUMB (1<<5)
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#define SR_FIQ (1<<6)
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#define SR_IRQ (1<<7)
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#ifdef ARM9
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#define CR_ENABLE_MPU (1<<0)
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#define CR_ENABLE_BIGEND (1<<7)
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#define CR_ENABLE_DCACHE (1<<2)
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#define CR_ENABLE_ICACHE (1<<12)
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#define CR_ENABLE_DTCM (1<<16)
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#define CR_ENABLE_ITCM (1<<18)
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#define CR_ALT_VECTORS (1<<13)
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#define CR_CACHE_RROBIN (1<<14)
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#define CR_DISABLE_TBIT (1<<15)
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#define CR_DTCM_LMODE (1<<17)
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#define CR_ITCM_LMODE (1<<19)
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#endif
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