2016-02-13 17:29:56 +01:00
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#ifdef EXEC_GATEWAY
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2016-04-11 14:11:34 +02:00
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.section .text.start
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2016-02-13 17:29:56 +01:00
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.global _start
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2016-04-11 14:11:34 +02:00
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.align 4
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2016-02-13 17:29:56 +01:00
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.arm
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_vectors:
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ldr pc, =InfiniteLoop
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.pool
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ldr pc, =InfiniteLoop
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.pool
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ldr pc, =InfiniteLoop
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.pool
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ldr pc, =InfiniteLoop
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.pool
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ldr pc, =InfiniteLoop
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.pool
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ldr pc, =InfiniteLoop
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.pool
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_start:
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ldr sp,=0x22140000
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@@wait for the arm11 kernel threads to be ready
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ldr r1, =0x10000
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waitLoop9:
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sub r1, #1
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cmp r1, #0
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bgt waitLoop9
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ldr r1, =0x10000
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waitLoop92:
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sub r1, #1
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cmp r1, #0
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bgt waitLoop92
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2016-04-11 01:58:18 +02:00
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@ Enable caches
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mrc p15, 0, r4, c1, c0, 0 @ read control register
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orr r4, r4, #(1<<18) @ - itcm enable
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orr r4, r4, #(1<<12) @ - instruction cache enable
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orr r4, r4, #(1<<2) @ - data cache enable
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orr r4, r4, #(1<<0) @ - mpu enable
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mcr p15, 0, r4, c1, c0, 0 @ write control register
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2016-02-13 17:29:56 +01:00
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ldr sp,=0x22160000
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ldr r3, =main
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blx r3
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.pool
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InfiniteLoop:
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b InfiniteLoop
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#endif // EXEC_GATEWAY
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