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Updated start.s file

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... may fix those very rarely happening freezes
This commit is contained in:
d0k3 2017-03-17 15:29:32 +01:00
parent 243f98a3f2
commit a20cd72a76
1 changed files with 7 additions and 7 deletions
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14
source/start.s
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@ -83,7 +83,7 @@ _skip_gw:
@ Clear bss @ Clear bss
ldr r0, =__bss_start ldr r0, =__bss_start
ldr r1, =__end__ ldr r1, =__bss_end
mov r2, #0 mov r2, #0
.bss_clr: .bss_clr:
@ -91,6 +91,12 @@ _skip_gw:
strlt r2, [r0], #4 strlt r2, [r0], #4
blt .bss_clr blt .bss_clr
@ Flush caches
mov r5, #0
mcr p15, 0, r5, c7, c5, 0 @ flush I-cache
mcr p15, 0, r5, c7, c6, 0 @ flush D-cache
mcr p15, 0, r5, c7, c10, 4 @ drain write buffer
@ Give read/write access to all the memory regions @ Give read/write access to all the memory regions
ldr r5, =0x33333333 ldr r5, =0x33333333
mcr p15, 0, r5, c5, c0, 2 @ write data access mcr p15, 0, r5, c5, c0, 2 @ write data access
@ -131,12 +137,6 @@ _skip_gw:
orr r4, r4, #(1<<0) @ - mpu enable orr r4, r4, #(1<<0) @ - mpu enable
mcr p15, 0, r4, c1, c0, 0 @ write control register mcr p15, 0, r4, c1, c0, 0 @ write control register
@ Flush caches
mov r5, #0
mcr p15, 0, r5, c7, c5, 0 @ flush I-cache
mcr p15, 0, r5, c7, c6, 0 @ flush D-cache
mcr p15, 0, r5, c7, c10, 4 @ drain write buffer
@ Fixes mounting of SDMC @ Fixes mounting of SDMC
ldr r0, =0x10000020 ldr r0, =0x10000020
mov r1, #0x340 mov r1, #0x340