mirror of
https://github.com/d0k3/GodMode9.git
synced 2025-06-26 13:42:47 +00:00
70757e3385
- moved all SPI code to the ARM11 - reimplemented NVRAM reading for the new SPI interface
121 lines
2.7 KiB
C
Executable File
121 lines
2.7 KiB
C
Executable File
// Somewhat based on xerpi's SPI driver for Linux
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// Original comment follows:
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/*
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* nintendo3ds_spi.c
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*
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* Copyright (C) 2016 Sergi Granell (xerpi)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <types.h>
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#include "hw/spi.h"
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#define REG_CFG_SPI_CNT ((vu16*)0x101401C0)
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#define REG_SPI(bus, reg) (*((vu32*)((bus) + (reg))))
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#define REG_SPI_BUS0 (0x10160800)
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#define REG_SPI_BUS1 (0x10142800)
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#define REG_SPI_BUS2 (0x10143800)
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#define REG_SPI_CONTROL 0x00
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#define REG_SPI_DONE 0x04
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#define REG_SPI_BLKLEN 0x08
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#define REG_SPI_FIFO 0x0C
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#define REG_SPI_STAT 0x10
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#define SPI_CONTROL_RATE(n) (n)
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#define SPI_CONTROL_CS(n) ((n) << 6)
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#define SPI_DIRECTION_READ (0)
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#define SPI_DIRECTION_WRITE BIT(13)
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#define SPI_CONTROL_BUSY BIT(15)
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#define SPI_CONTROL_START BIT(15)
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#define SPI_STAT_BUSY BIT(0)
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#define SPI_FIFO_WIDTH (32)
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static struct {
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u32 bus;
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u32 reg;
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} SPI_Devices[] = {
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{REG_SPI_BUS0, SPI_CONTROL_RATE(2) | SPI_CONTROL_CS(0)},
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{REG_SPI_BUS0, SPI_CONTROL_RATE(0) | SPI_CONTROL_CS(1)}, // NVRAM
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{REG_SPI_BUS0, SPI_CONTROL_RATE(0) | SPI_CONTROL_CS(2)},
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{REG_SPI_BUS1, SPI_CONTROL_RATE(5) | SPI_CONTROL_CS(0)}, // CODEC
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// TODO: complete this table
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};
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static void SPI_WaitBusy(u32 bus)
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{
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while(REG_SPI(bus, REG_SPI_CONTROL) & SPI_CONTROL_BUSY);
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}
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static void SPI_WaitFIFO(u32 bus)
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{
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while(REG_SPI(bus, REG_SPI_STAT) & SPI_STAT_BUSY);
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}
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static void SPI_Done(u32 bus)
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{
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REG_SPI(bus, REG_SPI_DONE) = 0;
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}
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static void SPI_SingleXfer(u32 reg, u32 bus, u32 *buffer, u32 len, bool read)
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{
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u32 pos = 0;
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REG_SPI(bus, REG_SPI_BLKLEN) = len;
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REG_SPI(bus, REG_SPI_CONTROL) = reg |
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(read ? SPI_DIRECTION_READ : SPI_DIRECTION_WRITE) | SPI_CONTROL_START;
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SPI_WaitFIFO(bus);
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do {
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if ((pos % SPI_FIFO_WIDTH) == 0)
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SPI_WaitFIFO(bus);
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if (read) {
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buffer[pos / 4] = REG_SPI(bus, REG_SPI_FIFO);
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} else {
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REG_SPI(bus, REG_SPI_FIFO) = buffer[pos / 4];
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}
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pos += 4;
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} while(pos < len);
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}
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int SPI_DoXfer(u32 dev, const SPI_XferInfo *xfers, u32 xfer_cnt)
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{
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u32 bus, reg;
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bus = SPI_Devices[dev].bus;
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reg = SPI_Devices[dev].reg;
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for (u32 i = 0; i < xfer_cnt; i++) {
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const SPI_XferInfo *xfer = &xfers[i];
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if (!xfer->buf || !xfer->len)
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continue;
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SPI_WaitBusy(bus);
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SPI_SingleXfer(reg, bus, xfer->buf, xfer->len, xfer->read);
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}
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SPI_WaitBusy(bus);
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SPI_Done(bus);
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return 0;
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}
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void SPI_Init(void)
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{
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// This cuts off access from the old SPI
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// interface used during the NDS days
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*REG_CFG_SPI_CNT = 7;
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}
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