mirror of
https://github.com/d0k3/GodMode9.git
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125 lines
2.6 KiB
ArmAsm
125 lines
2.6 KiB
ArmAsm
/*
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* This file is part of GodMode9
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* Copyright (C) 2017-2019 Wolfvak
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* This is almost the same as the ARM9 exception handler,
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* but with a few extra register dumps (DFSR, IFSR and FAR)
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*/
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#include <arm.h>
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.arm
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.align 3
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.macro TRAP_ENTRY xrq
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msr cpsr_f, #(\xrq << 29)
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b XRQ_Main
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.endm
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.section .vector, "ax"
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vectors:
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b XRQ_Reset
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b XRQ_Undefined
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b XRQ_SVC
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b XRQ_PrefetchAbt
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b XRQ_DataAbt
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b XRQ_Reserved
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b XRQ_IRQ
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b XRQ_FIQ
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XRQ_Reset:
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TRAP_ENTRY 0
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XRQ_Undefined:
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TRAP_ENTRY 1
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XRQ_SVC:
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TRAP_ENTRY 2
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XRQ_PrefetchAbt:
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TRAP_ENTRY 3
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XRQ_DataAbt:
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TRAP_ENTRY 4
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XRQ_Reserved:
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TRAP_ENTRY 5
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XRQ_FIQ:
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TRAP_ENTRY 7
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XRQ_Main:
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ldr sp, =(exception_stack_top - 32*4)
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stmia sp, {r0-r7}
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cpsid aif
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mrs r1, cpsr
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lsr r0, r1, #29
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mrs r2, spsr
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str lr, [sp, #15*4]
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str r2, [sp, #16*4]
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ands r2, r2, #SR_PMODE_MASK
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orreq r2, r2, #SR_SYS_MODE
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orr r2, r2, #(0x10 | SR_NOINT)
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add r3, sp, #8*4
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msr cpsr_c, r2
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nop
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nop
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stmia r3!, {r8-r14}
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nop
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nop
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msr cpsr_c, r1
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mrc p15, 0, r4, c5, c0, 0 @ data fault status register
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mrc p15, 0, r5, c5, c0, 1 @ instruction fault status register
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mrc p15, 0, r6, c6, c0, 0 @ data fault address
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add r3, r3, #2*4 @ skip saved PC and CPSR
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stmia r3!, {r4, r5, r6}
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mov r1, sp
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bl do_exception
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XRQ_IRQ:
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sub lr, lr, #4 @ Fix return address
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srsfd sp!, #SR_SVC_MODE @ Store IRQ mode LR and SPSR on the SVC stack
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cps #SR_SVC_MODE @ Switch to SVC mode
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push {r0-r4, r12, lr} @ Preserve registers
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and r4, sp, #7 @ Fix SP to be 8byte aligned
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sub sp, sp, r4
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mov lr, pc
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ldr pc, =gicTopHandler
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add sp, sp, r4
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pop {r0-r4, r12, lr}
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rfeia sp! @ Return from exception
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.section .bss.xrq_stk
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.align 12
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exception_stack: @ reserve a single aligned page for the exception stack
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.space 4096
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exception_stack_top:
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.global exception_stack_top
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