mirror of
https://github.com/d0k3/GodMode9.git
synced 2025-06-26 13:42:47 +00:00
Improved MPcore interrupt handler
This commit is contained in:
Wolfvak
d0k3
parent
e36b2c347f
commit
930b646008
12
Makefile
12
Makefile
@ -28,13 +28,12 @@ INCLUDES := common source source/common source/font source/filesys source/crypto
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#---------------------------------------------------------------------------------
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# options for code generation
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#---------------------------------------------------------------------------------
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ARCH := -mthumb -mthumb-interwork -flto
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ARCH := -DARM9 -march=armv5te -mthumb -mthumb-interwork -flto
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CFLAGS := -g -Wall -Wextra -Wpedantic -Wcast-align -Wno-main -O2\
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-march=armv5te -mtune=arm946e-s -fomit-frame-pointer -ffast-math -std=gnu11\
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$(ARCH)
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CFLAGS += $(INCLUDE) -DARM9
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ASFLAGS := $(ARCH) -g -x assembler-with-cpp $(INCLUDE)
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CFLAGS := $(ARCH) -g -Wall -Wextra -Wpedantic -Wcast-align -Wno-main -O2 \
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-mtune=arm946e-s -fomit-frame-pointer -ffast-math -std=gnu11 \
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$(INCLUDE)
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CFLAGS += -DBUILD_NAME="\"$(TARGET) (`date +'%Y/%m/%d'`)\""
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@ -64,7 +63,6 @@ endif
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CXXFLAGS := $(CFLAGS) -fno-rtti -fno-exceptions
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ASFLAGS := -g $(ARCH)
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LDFLAGS = -T../link.ld -nostartfiles -g $(ARCH) -Wl,-Map,$(TARGET).map
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LIBS :=
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15
common/arm.h
Normal file
15
common/arm.h
Normal file
@ -0,0 +1,15 @@
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#pragma once
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/* Status Register flags */
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#define SR_USR_MODE (0x10)
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#define SR_FIQ_MODE (0x11)
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#define SR_IRQ_MODE (0x12)
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#define SR_SVC_MODE (0x13)
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#define SR_ABT_MODE (0x17)
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#define SR_UND_MODE (0x1B)
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#define SR_SYS_MODE (0x1F)
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#define SR_PMODE_MASK (0x1F)
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#define SR_THUMB (1 << 5)
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#define SR_FIQ (1 << 6)
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#define SR_IRQ (1 << 7)
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@ -7,6 +7,7 @@
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#endif
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#include <stdint.h>
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#include <stddef.h>
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#define BIT(x) (1<<(x))
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@ -12,10 +12,12 @@ dir_source := source
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dir_build := build
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dir_out := ../$(dir_build)
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ASFLAGS := -mcpu=mpcore -mfloat-abi=soft
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CFLAGS := -DARM11 -Wall -Wextra -MMD -MP -marm -mno-thumb-interwork \
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$(ASFLAGS) -fno-builtin -std=c11 -Wno-main -O2 -flto -ffast-math \
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-I$(dir_source) -I../common
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ARCH := -DARM11 -mcpu=mpcore -mfloat-abi=soft -marm -mno-thumb-interwork
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INCLUDE := -I$(dir_source) -I../common
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ASFLAGS := $(ARCH) -x assembler-with-cpp $(INCLUDE)
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CFLAGS := $(ARCH) -Wall -Wextra -MMD -MP -fno-builtin \
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-std=c11 -O2 -flto -ffast-math -Wno-main $(INCLUDE)
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LDFLAGS := -nostdlib -nostartfiles
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objects = $(patsubst $(dir_source)/%.s, $(dir_build)/%.o, \
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@ -37,8 +39,8 @@ $(dir_out)/$(name).elf: $(objects)
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$(dir_build)/%.o: $(dir_source)/%.c
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@mkdir -p "$(@D)"
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$(COMPILE.c) $(OUTPUT_OPTION) $<
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$(CC) -c $(CFLAGS) -o $@ $<
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$(dir_build)/%.o: $(dir_source)/%.s
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@mkdir -p "$(@D)"
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$(COMPILE.s) $(OUTPUT_OPTION) $<
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$(CC) -c $(ASFLAGS) -o $@ $<
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@ -6,13 +6,12 @@ SECTIONS
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{
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. = 0x1FF80000;
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.text : ALIGN(4) { *(.text.start) *(.text*); . = ALIGN(4); }
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.text : ALIGN(4) { *(.text.boot) *(.text*); . = ALIGN(4); }
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.rodata : ALIGN(4) { *(.rodata*); . = ALIGN(4); }
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.data : ALIGN(4) { *(.data*); . = ALIGN(8); *(.bss* COMMON); . = ALIGN(8); }
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.bss : ALIGN(4) { __bss_start = .; *(.bss*); __bss_end = .; }
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. = ALIGN(4);
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__irq_stack = 0x1FFFF800;
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__prg_stack = 0x1FFFF400;
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__stack_top = 0x1FFFF800;
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}
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@ -3,10 +3,12 @@
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.section .text.boot
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.arm
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#include <arm.h>
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.global __boot
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__boot:
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@ Disable interrupts and switch to IRQ
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cpsid aif, #0x12
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cpsid aif, #(SR_SVC_MODE)
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@ Writeback and invalidate caches
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mov r0, #0
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@ -14,11 +16,7 @@ __boot:
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mcr p15, 0, r0, c7, c14, 0
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mcr p15, 0, r0, c7, c10, 4
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ldr sp, =__irq_stack
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@ Switch to SVC
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cpsid aif, #0x13
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ldr sp, =__prg_stack
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ldr sp, =__stack_top
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@ Reset values
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ldr r0, =0x00054078
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@ -10,18 +10,17 @@
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#define IRQ_BASE ((vu32*)0x1FFFFFA0)
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irq_handler handler_table[MAX_IRQ];
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extern void (*main_irq_handler)(void);
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void __attribute__((interrupt("IRQ"))) gic_irq_handler(void)
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irq_handler GIC_AckIRQ(void)
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{
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u32 xrq, ss;
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CPU_EnterCritical(&ss);
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xrq = *GIC_IRQACK;
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u32 xrq = *GIC_IRQACK;
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irq_handler ret = NULL;
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if (xrq < MAX_IRQ && handler_table[xrq]) {
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(handler_table[xrq])(xrq);
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}
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ret = handler_table[xrq];
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*GIC_IRQEND = xrq;
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CPU_LeaveCritical(&ss);
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return;
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}
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return ret;
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}
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void GIC_Configure(u32 irq_id, irq_handler hndl)
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@ -35,23 +34,30 @@ void GIC_Configure(u32 irq_id, irq_handler hndl)
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void GIC_Reset(void)
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{
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*DIC_CONTROL = 0;
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*GIC_CONTROL = 0;
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*GIC_PRIOMASK = ~0;
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for (int i = 0; i < (BIT(9)-1); i++) {
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*GIC_IRQEND |= i;
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*GIC_PRIOMASK = ~0;
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for (int i = 0; i < 0x80; i++) {
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*GIC_IRQEND = i;
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}
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*DIC_CONTROL = 0;
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for (int i = 0; i < (0x20/4); i++) {
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DIC_CLRENABLE[i] = ~0;
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DIC_PRIORITY[i] = 0;
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}
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*DIC_CONTROL = 1;
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*GIC_CONTROL = 1;
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while(*GIC_PENDING != SPURIOUS_IRQ) {
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for (int i=0; i < (0x20/4); i++) {
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DIC_CLRPENDING[i] = ~0;
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}
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}
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IRQ_BASE[1] = (u32)gic_irq_handler;
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IRQ_BASE[1] = (u32)&main_irq_handler;
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IRQ_BASE[0] = 0xE51FF004;
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*GIC_CONTROL = 1;
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*DIC_CONTROL = 1;
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return;
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}
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@ -6,51 +6,29 @@
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#pragma once
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#include <types.h>
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typedef void (*irq_handler)(u32);
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typedef void (*irq_handler)(void);
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#define MAX_IRQ (0x80)
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#define SPURIOUS_IRQ (1023)
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#define GIC_BASE (0x17E00100)
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#define DIC_BASE (0x17E01000)
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/* Setting bit 0 enables the GIC */
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#define GIC_CONTROL ((vu32*)(GIC_BASE + 0x00))
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/* Bits [7:0] control the min priority accepted */
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#define GIC_PRIOMASK ((vu32*)(GIC_BASE + 0x04))
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/* When an IRQ occurrs, this register holds the IRQ ID */
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#define GIC_IRQACK ((vu32*)(GIC_BASE + 0x0C))
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/* Write the IRQ ID here to acknowledge it */
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#define GIC_IRQEND ((vu32*)(GIC_BASE + 0x10))
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#define GIC_PENDING ((vu32*)(GIC_BASE + 0x18))
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/* Setting bit 0 enables the DIC */
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#define DIC_CONTROL ((vu32*)(DIC_BASE + 0x000))
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/*
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Write here to enable an IRQ ID
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The register address is DIC_SETENABLE + (N/32)*4 and its
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corresponding bit index is (N%32)
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*/
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#define DIC_SETENABLE ((vu32*)(DIC_BASE + 0x100))
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/* same as above but disables the IRQ */
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#define DIC_CLRENABLE ((vu32*)(DIC_BASE + 0x180))
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/* sets the IRQ priority */
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#define DIC_SETPENDING ((vu32*)(DIC_BASE + 0x200))
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#define DIC_CLRPENDING ((vu32*)(DIC_BASE + 0x280))
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#define DIC_PRIORITY ((vu32*)(DIC_BASE + 0x400))
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/* specifies which CPUs are allowed to be forwarded the IRQ */
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#define DIC_PROCTGT ((vu8*) (DIC_BASE + 0x800))
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/*
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each irq has 2 bits assigned
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bit 0 = 0: uses 1-N model
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1: uses N-N model
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bit 1 = 0: level high active
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1: rising edge sensitive
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*/
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#define DIC_CFGREG ((vu32*)(DIC_BASE + 0xC00))
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void gic_irq_handler(void);
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void GIC_Configure(u32 irq_id, irq_handler hndl);
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void GIC_Reset(void);
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29
screeninit/source/irq.s
Normal file
29
screeninit/source/irq.s
Normal file
@ -0,0 +1,29 @@
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.section .text
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.arm
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#include <arm.h>
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.global main_irq_handler
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.type main_irq_handler, %function
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main_irq_handler:
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sub lr, lr, #4 @ Fix return address
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srsdb sp!, #(SR_SVC_MODE) @ Store IRQ mode LR and SPSR on the SVC stack
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cps #(SR_SVC_MODE) @ Switch to SVC mode
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push {r0-r3,r12} @ Preserve registers
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and r1, sp, #4
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sub sp, sp, r1 @ Word-align stack
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push {r1,lr}
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bl GIC_AckIRQ @ Acknowledge interrupt, get handler address
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cmp r0, #0
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beq .Lskip_irq
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cpsie i
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blx r0 @ Branch to interrupt handler with IRQs enabled
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cpsid i
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.Lskip_irq:
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pop {r1,lr}
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add sp, sp, r1 @ Restore stack pointer
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pop {r0-r3,lr} @ Restore registers
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rfeia sp! @ Return From Exception
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@ -133,7 +133,7 @@ void set_brightness(u8 brightness)
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*(vu32 *)0x10202A40 = brightness;
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}
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void pxi_interrupt_handler(__attribute__((unused)) u32 xrq_n)
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void pxi_interrupt_handler(void)
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{
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u8 msg = PXI_GetRemote();
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switch(msg) {
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@ -2,11 +2,13 @@
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.align 4
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.arm
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#include <arm.h>
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@ make sure not to clobber r0-r2
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.global _start
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_start:
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@ Switch to supervisor mode and disable interrupts
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msr cpsr_c, #0xD3
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msr cpsr_c, #(SR_SVC_MODE | SR_IRQ | SR_FIQ)
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@ Short delay (not always necessary, just in case)
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mov r3, #0x40000
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