mirror of
https://github.com/d0k3/GodMode9.git
synced 2025-06-26 13:42:47 +00:00
Potentially fix screen init on some systems
Sanitized I2C Reorganized the memory layout - Moved GM9 to ARM9 RAM - Increased RAMdisk size to 88MiB
This commit is contained in:
Wolfvak
parent
5e652b1313
commit
8a4597635d
10
Makefile
10
Makefile
@ -74,7 +74,7 @@ endif
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CXXFLAGS := $(CFLAGS) -fno-rtti -fno-exceptions
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LDFLAGS = -T../link.ld -nostartfiles -g $(ARCH) -Wl,-Map,$(TARGET).map
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LDFLAGS = -T../link.ld -nostartfiles -g $(ARCH) -Wl,-Map,$(TARGET).map,-z,max-page-size=512
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LIBS :=
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@ -152,12 +152,12 @@ binary: common
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@$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile
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firm: binary screeninit
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firmtool build $(OUTPUT).firm -n 0x08006000 -A 0x08006000 -D $(OUTPUT).bin $(OUTPUT_D)/screeninit.elf -C NDMA XDMA -S nand-retail -g
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firmtool build $(OUTPUT)_dev.firm -n 0x08006000 -A 0x08006000 -D $(OUTPUT).bin $(OUTPUT_D)/screeninit.elf -C NDMA XDMA -S nand-dev -g
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firmtool build $(OUTPUT).firm -D $(OUTPUT).elf $(OUTPUT_D)/screeninit.elf -C NDMA XDMA -S nand-retail -g
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firmtool build $(OUTPUT)_dev.firm -D $(OUTPUT).elf $(OUTPUT_D)/screeninit.elf -C NDMA XDMA -S nand-dev -g
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ntrboot: binary screeninit
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firmtool build $(OUTPUT)_ntr.firm -n 0x08006000 -A 0x08006000 -D $(OUTPUT).bin $(OUTPUT_D)/screeninit.elf -C NDMA XDMA -S spi-retail -g
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firmtool build $(OUTPUT)_ntr_dev.firm -n 0x08006000 -A 0x08006000 -D $(OUTPUT).bin $(OUTPUT_D)/screeninit.elf -C NDMA XDMA -S spi-dev -g
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firmtool build $(OUTPUT)_ntr.firm -D $(OUTPUT).elf $(OUTPUT_D)/screeninit.elf -C NDMA XDMA -S spi-retail -g
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firmtool build $(OUTPUT)_ntr_dev.firm -D $(OUTPUT).elf $(OUTPUT_D)/screeninit.elf -C NDMA XDMA -S spi-dev -g
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release:
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@-rm -fr $(BUILD) $(OUTPUT_D) $(RELEASE)
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@ -18,6 +18,7 @@ enum {
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PXI_NONE = 0,
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PXI_READY,
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PXI_BUSY,
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PXI_SCREENINIT,
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PXI_BRIGHTNESS
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};
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6
link.ld
6
link.ld
@ -4,7 +4,7 @@ ENTRY(_start)
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SECTIONS
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{
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. = 0x23F00000;
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. = 0x08006000;
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__start__ = ABSOLUTE(.);
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.text.start : ALIGN(4) { *(.text.start) }
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@ -17,7 +17,7 @@ SECTIONS
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__end__ = ABSOLUTE(.);
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__stack_abt = __start__;
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__stack_top = __start__ - 0x80000;
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__stack_abt = 0x22800000;
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__stack_top = __stack_abt - 0x80000;
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__code_size__ = __end__ - __start__;
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}
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@ -19,7 +19,7 @@ ASFLAGS := $(ARCH) -x assembler-with-cpp $(INCLUDE)
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CFLAGS := $(ARCH) -Wall -Wextra -MMD -MP -fno-builtin \
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-Wno-unused-function -Wno-unused-variable \
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-std=c11 -O2 -flto -ffast-math -Wno-main $(INCLUDE)
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LDFLAGS := -nostdlib -nostartfiles
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LDFLAGS := -nostdlib -nostartfiles -Wl,-z,max-page-size=512
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objects = $(patsubst $(dir_source)/%.s, $(dir_build)/%.o, \
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$(patsubst $(dir_source)/%.c, $(dir_build)/%.o, \
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@ -1,7 +1,6 @@
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#include <cpu.h>
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#include <pxi.h>
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#include <gic.h>
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#include <i2c.h>
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#include <gpulcd.h>
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#include <vram.h>
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#include <types.h>
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@ -19,6 +18,21 @@ void PXI_IRQHandler(void)
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default:
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break;
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case PXI_SCREENINIT:
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{
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GPU_Init();
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GPU_PSCFill(VRAM_START, VRAM_END, 0);
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GPU_SetFramebuffers((u32[]){VRAM_TOP_LA, VRAM_TOP_LB,
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VRAM_TOP_RA, VRAM_TOP_RB,
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VRAM_BOT_A, VRAM_BOT_B});
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GPU_SetFramebufferMode(0, PDC_RGB24);
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GPU_SetFramebufferMode(1, PDC_RGB24);
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PXI_SetRemote(PXI_BUSY);
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break;
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}
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case PXI_BRIGHTNESS:
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{
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PXI_RecvArray(pxi_args, 1);
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@ -50,17 +64,6 @@ void main(void)
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u32 entry;
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PXI_Reset();
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GPU_Init();
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GPU_PSCFill(VRAM_START, VRAM_END, 0);
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GPU_SetFramebuffers((u32[]){VRAM_TOP_LA, VRAM_TOP_LB,
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VRAM_TOP_RA, VRAM_TOP_RB,
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VRAM_BOT_A, VRAM_BOT_B});
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GPU_SetFramebufferMode(0, PDC_RGB24);
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GPU_SetFramebufferMode(1, PDC_RGB24);
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I2C_writeReg(I2C_DEV_MCU, 0x22, 0x2A);
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GIC_Reset();
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GIC_SetIRQ(IRQ_PXI_SYNC, PXI_IRQHandler);
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PXI_EnableIRQ();
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@ -91,6 +91,6 @@
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#define TEMP_BUFFER_SIZE (0x1800000) // 24MB(!)
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// buffer area defines (in use by image.c, for RAMdrive)
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#define RAMDRV_BUFFER ((u8*)0x24000000) // top half of FCRAM
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#define RAMDRV_SIZE_O3DS (0x04000000) // 64MB
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#define RAMDRV_SIZE_N3DS (0x0C000000) // 192MB
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#define RAMDRV_BUFFER ((u8*)0x22800000) // top of STACK
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#define RAMDRV_SIZE_O3DS (0x5800000) // 88MB
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#define RAMDRV_SIZE_N3DS (0xD800000) // 216MB
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@ -1,6 +1,7 @@
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#include "godmode.h"
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#include "power.h"
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#include "pxi.h"
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#include "i2c.h"
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void main(int argc, char** argv)
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{
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@ -9,13 +10,17 @@ void main(int argc, char** argv)
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// Wait for ARM11
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PXI_WaitRemote(PXI_READY);
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PXI_DoCMD(PXI_SCREENINIT, NULL, 0);
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I2C_writeReg(I2C_DEV_MCU, 0x22, 0x2A);
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#ifdef AUTORUN_SCRIPT
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// Run the script runner
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if (ScriptRunner(argc) == GODMODE_EXIT_REBOOT) Reboot();
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else PowerOff();
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if (ScriptRunner(argc) == GODMODE_EXIT_REBOOT)
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#else
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// Run the main program
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if (GodMode(argc) == GODMODE_EXIT_REBOOT) Reboot();
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else PowerOff();
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if (GodMode(argc) == GODMODE_EXIT_REBOOT)
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#endif
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Reboot();
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PowerOff();
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}
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156
source/start.s
156
source/start.s
@ -5,91 +5,50 @@
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#include <arm.h>
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#include <brf.h>
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@ Make sure to preserve r0-r2
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.global _start
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_start:
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@ Switch to supervisor mode and disable interrupts
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msr cpsr_c, #(SR_SYS_MODE | SR_IRQ | SR_FIQ)
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@ Disable interrupts
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mrs r4, cpsr
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orr r4, r4, #(SR_IRQ | SR_FIQ)
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msr cpsr_c, r4
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@ Short delay (not always necessary, just in case)
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mov r3, #0x40000
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.Lwaitloop:
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subs r3, #1
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bgt .Lwaitloop
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@ Check the load address
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adr r3, _start
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ldr r4, =__start__
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cmp r3, r4
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beq _start_gm
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@ Relocate the binary to the correct location and branch to it
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ldr r5, =__code_size__
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.Lbincopyloop:
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subs r5, #4
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ldrge r6, [r3, r5]
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strge r6, [r4, r5]
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bge .Lbincopyloop
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mov r5, r0
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mov r6, r1
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mov r7, r2
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ldr r3, =BRF_WB_INV_DCACHE
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blx r3
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mov r0, r5
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mov r1, r6
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mov r2, r7
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mov lr, #0
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mcr p15, 0, lr, c7, c5, 0 @ Invalidate ICache
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bx r4
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_start_gm:
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ldr sp, =__stack_top
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mov r9, r0 @ argc
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mov r10, r1 @ argv
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ldr r4, =0xBEEF
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lsl r2, #16
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lsr r2, #16
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cmp r2, r4 @ magic word
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movne r9, #0
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@ Disable caches / mpu
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ldr r1, =(CR_ENABLE_MPU | CR_ENABLE_DCACHE | CR_ENABLE_ICACHE | \
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CR_ENABLE_DTCM)
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ldr r2, =(CR_ENABLE_ITCM | CR_CACHE_RROBIN)
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r1
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orr r0, r2
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mcr p15, 0, r0, c1, c0, 0
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@ Preserve boot registers
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mov r9, r0
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mov r10, r1
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mov r11, r2
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@ Clear bss
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ldr r0, =__bss_start
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ldr r1, =__bss_end
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mov r2, #0
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.Lbss_clr:
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.LBSS_Clear:
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cmp r0, r1
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strlt r2, [r0], #4
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blt .Lbss_clr
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strlo r2, [r0], #4
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blo .LBSS_Clear
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@ Invalidate caches
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mov r5, #0
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mcr p15, 0, r5, c7, c5, 0 @ invalidate I-cache
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mcr p15, 0, r5, c7, c6, 0 @ invalidate D-cache
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mcr p15, 0, r5, c7, c10, 4 @ drain write buffer
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ldr r0, =BRF_WB_INV_DCACHE
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blx r0 @ Writeback & Invalidate Data Cache
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ldr r0, =BRF_INVALIDATE_ICACHE
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blx r0 @ Invalidate Instruction Cache
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@ Give read/write access to all the memory regions
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ldr r5, =0x33333333
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mcr p15, 0, r5, c5, c0, 2 @ write data access
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mcr p15, 0, r5, c5, c0, 3 @ write instruction access
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@ Disable caches / DTCM / MPU
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ldr r1, =(CR_ENABLE_MPU | CR_ENABLE_DCACHE | CR_ENABLE_ICACHE | \
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CR_ENABLE_DTCM)
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ldr r2, =(CR_ENABLE_ITCM)
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r1
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orr r0, r2
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mcr p15, 0, r0, c1, c0, 0
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@ Sets MPU regions and cache settings
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@ Give full access to defined memory regions
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ldr r0, =0x33333333
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mcr p15, 0, r0, c5, c0, 2 @ write data access
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mcr p15, 0, r0, c5, c0, 3 @ write instruction access
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@ Set MPU regions and cache settings
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adr r0, __mpu_regions
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ldmia r0, {r1-r8}
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mov r0, #0b00101101 @ bootrom/itcm/arm9 mem and fcram are cacheable/bufferable
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mov r0, #0b00101000
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mcr p15, 0, r1, c6, c0, 0
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mcr p15, 0, r2, c6, c1, 0
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mcr p15, 0, r3, c6, c2, 0
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@ -98,13 +57,22 @@ _start_gm:
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mcr p15, 0, r6, c6, c5, 0
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mcr p15, 0, r7, c6, c6, 0
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mcr p15, 0, r8, c6, c7, 0
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mcr p15, 0, r0, c3, c0, 0 @ Write bufferable 0, 2, 5
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mcr p15, 0, r0, c2, c0, 0 @ Data cacheable 0, 2, 5
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mcr p15, 0, r0, c2, c0, 1 @ Inst cacheable 0, 2, 5
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mcr p15, 0, r0, c3, c0, 0 @ Write bufferable
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mcr p15, 0, r0, c2, c0, 0 @ Data cacheable
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mcr p15, 0, r0, c2, c0, 1 @ Inst cacheable
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@ Enable dctm
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ldr r0, =0x3000800A @ set dtcm
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mcr p15, 0, r0, c9, c1, 0 @ set the dtcm Region Register
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ldr r0, =0x3000800A
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mcr p15, 0, r0, c9, c1, 0 @ set the DTCM Region Register
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@ Enable caches / select low exception vectors
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ldr r1, =(CR_ALT_VECTORS | CR_DISABLE_TBIT)
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ldr r2, =(CR_ENABLE_MPU | CR_ENABLE_DCACHE | CR_ENABLE_ICACHE | \
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CR_ENABLE_DTCM | CR_CACHE_RROBIN)
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r1
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orr r0, r2
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mcr p15, 0, r0, c1, c0, 0
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@ Install exception handlers
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ldr r0, =XRQ_Start
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@ -112,28 +80,30 @@ _start_gm:
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ldr r2, =0x00000000
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.LXRQ_Install:
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cmp r0, r1
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ldrlt r3, [r0], #4
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strlt r3, [r2], #4
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blt .LXRQ_Install
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ldrlo r3, [r0], #4
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strlo r3, [r2], #4
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blo .LXRQ_Install
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@ Enable caches / select low exception vectors
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ldr r1, =(CR_ALT_VECTORS | CR_DISABLE_TBIT)
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ldr r2, =(CR_ENABLE_MPU | CR_ENABLE_DCACHE | CR_ENABLE_ICACHE | \
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CR_ENABLE_DTCM)
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r1
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orr r0, r2
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mcr p15, 0, r0, c1, c0, 0
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@ Fixes mounting of SDMC
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ldr r0, =0x10000000
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@ Fix SDMC mounting
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mov r0, #0x10000000
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mov r1, #0x340
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str r1, [r0, #0x20]
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mov r0, r9
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mov r1, r10
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@ Check arguments
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lsl r2, r11, #16
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lsr r2, r2, #16
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bl main
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ldr r3, =0xBEEF
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cmp r2, r3
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moveq r0, r9
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moveq r1, r10
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movne r0, #0
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@ Switch to system mode, disable interrupts, setup application stack
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msr cpsr_c, #(SR_SYS_MODE | SR_IRQ | SR_FIQ)
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ldr sp, =__stack_top
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b main
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__mpu_regions:
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.word 0xFFFF001F @ FFFF0000 64k | bootrom (unprotected / protected)
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@ -16,39 +16,10 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <types.h>
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#include <stdbool.h>
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#include "i2c.h"
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#define I2C_STOP (1u)
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#define I2C_START (1u<<1)
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#define I2C_ERROR (1u<<2)
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#define I2C_ACK (1u<<4)
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#define I2C_DIRE_WRITE (0u)
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#define I2C_DIRE_READ (1u<<5)
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#define I2C_IRQ_ENABLE (1u<<6)
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#define I2C_ENABLE (1u<<7)
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#define I2C_GET_ACK(reg) ((bool)((reg)>>4 & 1u))
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typedef enum
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{
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I2C_DEV_POWER = 0, // Unconfirmed
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I2C_DEV_CAMERA = 1, // Unconfirmed
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I2C_DEV_CAMERA2 = 2, // Unconfirmed
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I2C_DEV_MCU = 3,
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I2C_DEV_GYRO = 10,
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I2C_DEV_DEBUG_PAD = 12,
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I2C_DEV_IR = 13,
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I2C_DEV_EEPROM = 14, // Unconfirmed
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I2C_DEV_NFC = 15,
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I2C_DEV_QTM = 16,
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I2C_DEV_N3DS_HID = 17
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} I2cDevice;
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#define I2C1_REGS_BASE (0x10161000)
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#define REG_I2C1_DATA *((vu8* )(I2C1_REGS_BASE + 0x00))
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#define REG_I2C1_CNT *((vu8* )(I2C1_REGS_BASE + 0x01))
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@ -94,12 +65,14 @@ static const struct
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{2, 0x54}
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};
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static inline void i2cWaitBusy(vu8 *cntReg)
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|
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static void i2cWaitBusy(vu8 *cntReg)
|
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{
|
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while(*cntReg & I2C_ENABLE);
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}
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static inline vu8* i2cGetBusRegsBase(u8 busId)
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static vu8* i2cGetBusRegsBase(u8 busId)
|
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{
|
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vu8 *base;
|
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if(!busId) base = (vu8*)I2C1_REGS_BASE;
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@ -161,7 +134,7 @@ static bool i2cStartTransfer(I2cDevice devId, u8 regAddr, bool read, vu8 *regsBa
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else return false;
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}
|
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|
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static void I2C_init(void)
|
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void I2C_init(void)
|
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{
|
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i2cWaitBusy(i2cGetBusRegsBase(0));
|
||||
REG_I2C1_CNTEX = 2; // ?
|
||||
@ -176,7 +149,7 @@ static void I2C_init(void)
|
||||
REG_I2C3_SCL = 1280; // ?
|
||||
}
|
||||
|
||||
static bool I2C_readRegBuf(I2cDevice devId, u8 regAddr, u8 *out, u32 size)
|
||||
bool I2C_readRegBuf(I2cDevice devId, u8 regAddr, u8 *out, u32 size)
|
||||
{
|
||||
const u8 busId = i2cDevTable[devId].busId;
|
||||
vu8 *const i2cData = i2cGetBusRegsBase(busId);
|
||||
@ -199,7 +172,7 @@ static bool I2C_readRegBuf(I2cDevice devId, u8 regAddr, u8 *out, u32 size)
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool I2C_writeReg(I2cDevice devId, u8 regAddr, u8 data)
|
||||
bool I2C_writeReg(I2cDevice devId, u8 regAddr, u8 data)
|
||||
{
|
||||
const u8 busId = i2cDevTable[devId].busId;
|
||||
vu8 *const i2cData = i2cGetBusRegsBase(busId);
|
||||
56
source/system/i2c.h
Normal file
56
source/system/i2c.h
Normal file
@ -0,0 +1,56 @@
|
||||
#pragma once
|
||||
|
||||
/*
|
||||
* This file is part of fastboot 3DS
|
||||
* Copyright (C) 2017 derrek, profi200
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include "common.h"
|
||||
|
||||
|
||||
#define I2C_STOP (1u)
|
||||
#define I2C_START (1u<<1)
|
||||
#define I2C_ERROR (1u<<2)
|
||||
#define I2C_ACK (1u<<4)
|
||||
#define I2C_DIRE_WRITE (0u)
|
||||
#define I2C_DIRE_READ (1u<<5)
|
||||
#define I2C_IRQ_ENABLE (1u<<6)
|
||||
#define I2C_ENABLE (1u<<7)
|
||||
|
||||
#define I2C_GET_ACK(reg) ((bool)((reg)>>4 & 1u))
|
||||
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2C_DEV_POWER = 0, // Unconfirmed
|
||||
I2C_DEV_CAMERA = 1, // Unconfirmed
|
||||
I2C_DEV_CAMERA2 = 2, // Unconfirmed
|
||||
I2C_DEV_MCU = 3,
|
||||
I2C_DEV_GYRO = 10,
|
||||
I2C_DEV_DEBUG_PAD = 12,
|
||||
I2C_DEV_IR = 13,
|
||||
I2C_DEV_EEPROM = 14, // Unconfirmed
|
||||
I2C_DEV_NFC = 15,
|
||||
I2C_DEV_QTM = 16,
|
||||
I2C_DEV_N3DS_HID = 17
|
||||
} I2cDevice;
|
||||
|
||||
|
||||
|
||||
void I2C_init(void);
|
||||
bool I2C_readRegBuf(I2cDevice devId, u8 regAddr, u8 *out, u32 size);
|
||||
bool I2C_writeReg(I2cDevice devId, u8 regAddr, u8 data);
|
||||
Loading…
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Reference in New Issue
Block a user