mirror of
https://github.com/d0k3/GodMode9.git
synced 2025-06-26 21:52:48 +00:00
revert back to using Thumb code for the ARM9 binary
leads to better density and therefore much smaller FIRM sizes
This commit is contained in:
Wolfvak
parent
929cc7fdcf
commit
3973ce57df
@ -5,7 +5,7 @@ TARGET := $(shell basename $(CURDIR))
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SOURCE := source
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BUILD := build
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SUBARCH := -D$(PROCESSOR) -marm -march=armv6k -mtune=mpcore -mfloat-abi=hard -mfpu=vfpv2 -mtp=soft
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SUBARCH := -D$(PROCESSOR) -march=armv6k -mtune=mpcore -marm -mfloat-abi=hard -mfpu=vfpv2 -mtp=soft
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INCDIRS := source
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INCLUDE := $(foreach dir,$(INCDIRS),-I"$(shell pwd)/$(dir)")
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@ -5,7 +5,7 @@ TARGET := $(shell basename $(CURDIR))
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SOURCE := source
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BUILD := build
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SUBARCH := -D$(PROCESSOR) -marm -march=armv5te -mtune=arm946e-s -mfloat-abi=soft -mno-thumb-interwork
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SUBARCH := -D$(PROCESSOR) -march=armv5te -mtune=arm946e-s -mthumb -mfloat-abi=soft
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INCDIRS := source source/common source/filesys source/crypto source/fatfs source/nand source/virtual source/game source/gamecart source/lodepng source/qrcodegen source/system source/utils
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INCLUDE := $(foreach dir,$(INCDIRS),-I"$(shell pwd)/$(dir)")
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@ -60,7 +60,7 @@ XRQ_DUMPDATAFUNC(u16, 4)
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XRQ_DUMPDATAFUNC(u32, 8)
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const char *XRQ_Name[] = {
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static const char *XRQ_Name[] = {
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"Reset", "Undefined", "SWI", "Prefetch Abort",
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"Data Abort", "Reserved", "IRQ", "FIQ"
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};
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@ -80,10 +80,9 @@ void XRQ_DumpRegisters(u32 xrq, u32 *regs)
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wstr += sprintf(wstr, "20%02lX-%02lX-%02lX %02lX:%02lX:%02lX\n \n",
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(u32) dstime.bcd_Y, (u32) dstime.bcd_M, (u32) dstime.bcd_D,
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(u32) dstime.bcd_h, (u32) dstime.bcd_m, (u32) dstime.bcd_s);
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for (int i = 0; i < 8; i++) {
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int i_ = i*2;
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for (int i = 0; i < 16; i += 2) {
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wstr += sprintf(wstr,
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"R%02d: %08lX | R%02d: %08lX\n", i_, regs[i_], i_+1, regs[i_+1]);
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"R%02d: %08lX | R%02d: %08lX\n", i, regs[i], i+1, regs[i+1]);
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}
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wstr += sprintf(wstr, "CPSR: %08lX\n\n", regs[16]);
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@ -110,11 +109,11 @@ void XRQ_DumpRegisters(u32 xrq, u32 *regs)
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if (pc_dumpable(pc, &pc_lower, &pc_upper)) {
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wstr += sprintf(wstr, "Code:\n");
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wstr += XRQ_DumpData_u32(wstr, pc_lower, pc_upper);
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/*if (regs[16] & SR_THUMB) { // no need to take Thumb code into account
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if (regs[16] & SR_THUMB) { // need to take Thumb code into account
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wstr += XRQ_DumpData_u16(wstr, pc-PC_DUMPRAD, pc+PC_DUMPRAD);
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} else {
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wstr += XRQ_DumpData_u32(wstr, pc-PC_DUMPRAD, pc+PC_DUMPRAD);
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}*/
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}
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}
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/* Draw QR Code */
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@ -127,7 +126,6 @@ void XRQ_DumpRegisters(u32 xrq, u32 *regs)
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DrawQrCode(ALT_SCREEN, qrcode);
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}
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/* Reinitialize SD */
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DrawStringF(MAIN_SCREEN, draw_x, draw_y_upd, COLOR_STD_FONT, COLOR_STD_BG,
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"%-29.29s", "Reinitializing SD card...");
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@ -146,7 +144,6 @@ void XRQ_DumpRegisters(u32 xrq, u32 *regs)
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"%-29.29s", "Dumping state to SD card...");
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FileSetData(path, dumpstr, wstr - dumpstr, 0, true);
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/* Deinit SD */
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DeinitSDCardFS();
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@ -156,7 +153,6 @@ void XRQ_DumpRegisters(u32 xrq, u32 *regs)
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while (!(InputWait(0) & BUTTON_POWER));
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PowerOff();
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/* We will not return */
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return;
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}
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230
common/arm.c
Normal file
230
common/arm.c
Normal file
@ -0,0 +1,230 @@
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#include <arm.h>
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#define ARM_TARGET __attribute__((noinline, target("arm")))
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#ifdef ARM11
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#define ARM_CPS(m) asm_v("CPS " #m)
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#define ARM_CPSID(m) asm_v("CPSID " #m)
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#define ARM_CPSIE(m) asm_v("CPSIE " #m)
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/*
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* An Instruction Synchronization Barrier (ISB) flushes the pipeline in the processor
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* so that all instructions following the ISB are fetched from cache or memory
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* after the ISB has been completed.
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*/
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void ARM_TARGET ARM_ISB(void) {
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ARM_MCR(p15, 0, 0, c7, c5, 4);
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}
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/*
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* A Data Memory Barrier (DMB) ensures that all explicit memory accesses before
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* the DMB instruction complete before any explicit memory accesses after the DMB instruction start.
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*/
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void ARM_TARGET ARM_DMB(void) {
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ARM_MCR(p15, 0, 0, c7, c10, 5);
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}
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/* Wait For Interrupt */
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void ARM_TARGET ARM_WFI(void) {
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asm_v("wfi\n\t");
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}
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/* Wait For Event */
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void ARM_TARGET ARM_WFE(void) {
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asm_v("wfe\n\t");
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}
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/* Send Event */
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void ARM_TARGET ARM_SEV(void) {
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asm_v("sev\n\t");
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}
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/* Auxiliary Control Registers */
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u32 ARM_TARGET ARM_GetACR(void) {
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u32 acr;
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ARM_MRC(p15, 0, acr, c1, c0, 1);
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return acr;
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}
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void ARM_TARGET ARM_SetACR(u32 acr) {
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ARM_MCR(p15, 0, acr, c1, c0, 1);
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}
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#endif
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/*
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* A Data Synchronization Barrier (DSB) completes when all
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* instructions before this instruction complete.
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*/
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void ARM_TARGET ARM_DSB(void) {
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ARM_MCR(p15, 0, 0, c7, c10, 4);
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}
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/* Control Registers */
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u32 ARM_TARGET ARM_GetCR(void) {
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u32 cr;
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ARM_MRC(p15, 0, cr, c1, c0, 0);
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return cr;
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}
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void ARM_TARGET ARM_SetCR(u32 cr) {
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ARM_MCR(p15, 0, cr, c1, c0, 0);
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}
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/* Thread ID Registers */
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u32 ARM_TARGET ARM_GetTID(void) {
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u32 tid;
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#ifdef ARM9
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ARM_MRC(p15, 0, tid, c13, c0, 1);
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#else
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ARM_MRC(p15, 0, tid, c13, c0, 4);
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#endif
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return tid;
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}
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void ARM_TARGET ARM_SetTID(u32 tid) {
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#ifdef ARM9
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ARM_MCR(p15, 0, tid, c13, c0, 1);
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#else
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ARM_MCR(p15, 0, tid, c13, c0, 4);
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#endif
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}
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/* CPU ID */
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u32 ARM_TARGET ARM_CoreID(void) {
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u32 id;
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#ifdef ARM9
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id = 0;
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#else
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ARM_MRC(p15, 0, id, c0, c0, 5);
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#endif
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return id & 3;
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}
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/* Status Register */
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u32 ARM_TARGET ARM_GetCPSR(void) {
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u32 sr;
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ARM_MRS(sr, cpsr);
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return sr;
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}
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void ARM_TARGET ARM_SetCPSR_c(u32 sr) {
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ARM_MSR(cpsr_c, sr);
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}
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void ARM_TARGET ARM_DisableInterrupts(void) {
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#ifdef ARM9
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ARM_SetCPSR_c(ARM_GetCPSR() | SR_NOINT);
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#else
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ARM_CPSID(if);
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#endif
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}
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void ARM_TARGET ARM_EnableInterrupts(void) {
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#ifdef ARM9
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ARM_SetCPSR_c(ARM_GetCPSR() & ~SR_NOINT);
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#else
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ARM_CPSIE(if);
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#endif
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}
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u32 ARM_TARGET ARM_EnterCritical(void) {
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u32 stat = ARM_GetCPSR();
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ARM_DisableInterrupts();
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return stat & SR_NOINT;
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}
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void ARM_TARGET ARM_LeaveCritical(u32 stat) {
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ARM_SetCPSR_c((ARM_GetCPSR() & ~SR_NOINT) | stat);
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}
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/* Cache functions */
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void ARM_TARGET ARM_InvIC(void) {
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#ifdef ARM9
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ARM_MCR(p15, 0, 0, c7, c5, 0);
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#else
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ARM_MCR(p15, 0, 0, c7, c7, 0);
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#endif
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}
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void ARM_TARGET ARM_InvIC_Range(void *base, u32 len) {
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u32 addr = (u32)base & ~0x1F;
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len >>= 5;
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do {
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#ifdef ARM9
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ARM_MCR(p15, 0, addr, c7, c5, 1);
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#else
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ARM_MCR(p15, 0, addr, c7, c7, 1);
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#endif
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addr += 0x20;
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} while(len--);
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}
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void ARM_TARGET ARM_InvDC(void) {
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ARM_MCR(p15, 0, 0, c7, c6, 0);
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}
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void ARM_TARGET ARM_InvDC_Range(void *base, u32 len) {
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u32 addr = (u32)base & ~0x1F;
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len >>= 5;
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do {
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ARM_MCR(p15, 0, addr, c7, c6, 1);
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addr += 0x20;
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} while(len--);
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}
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void ARM_TARGET ARM_WbDC(void) {
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#ifdef ARM9
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u32 seg = 0, ind;
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do {
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ind = 0;
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do {
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ARM_MCR(p15, 0, seg | ind, c7, c10, 2);
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ind += 0x20;
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} while(ind < 0x400);
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seg += 0x40000000;
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} while(seg != 0);
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#else
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ARM_MCR(p15, 0, 0, c7, c10, 0);
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#endif
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}
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void ARM_TARGET ARM_WbDC_Range(void *base, u32 len) {
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u32 addr = (u32)base & ~0x1F;
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len >>= 5;
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do {
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ARM_MCR(p15, 0, addr, c7, c10, 1);
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addr += 0x20;
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} while(len--);
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}
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void ARM_TARGET ARM_WbInvDC(void) {
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#ifdef ARM9
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u32 seg = 0, ind;
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do {
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ind = 0;
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do {
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ARM_MCR(p15, 0, seg | ind, c7, c14, 2);
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ind += 0x20;
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} while(ind < 0x400);
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seg += 0x40000000;
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} while(seg != 0);
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#else
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ARM_MCR(p15, 0, 0, c7, c14, 0);
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#endif
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}
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void ARM_TARGET ARM_WbInvDC_Range(void *base, u32 len) {
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u32 addr = (u32)base & ~0x1F;
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len >>= 5;
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do {
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ARM_MCR(p15, 0, addr, c7, c14, 1);
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addr += 0x20;
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} while(len--);
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}
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259
common/arm.h
259
common/arm.h
@ -69,12 +69,7 @@
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#ifndef __ASSEMBLER__
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/* ARM Private Memory Region */
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#ifdef ARM11
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#define REG_ARM_PMR(off, type) ((volatile type*)(0x17E00000 + (off)))
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#endif
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// only accessible from ARM mode
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#define ARM_MCR(cp, op1, reg, crn, crm, op2) asm_v( \
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"MCR " #cp ", " #op1 ", %[R], " #crn ", " #crm ", " #op2 "\n\t" \
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:: [R] "r"(reg) : "memory","cc")
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@ -91,232 +86,52 @@
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"MRS %[R], " #cp "\n\t" \
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: [R] "=r"(reg) :: "memory","cc")
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/* ARM Private Memory Region */
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#ifdef ARM11
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#define ARM_CPS(m) asm_v("CPS " #m)
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#define ARM_CPSID(m) asm_v("CPSID " #m)
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#define ARM_CPSIE(m) asm_v("CPSIE " #m)
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#define REG_ARM_PMR(off, type) ((volatile type*)(0x17E00000 + (off)))
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/*
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* An Instruction Synchronization Barrier (ISB) flushes the pipeline in the processor
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* so that all instructions following the ISB are fetched from cache or memory
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* after the ISB has been completed.
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*/
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static inline void ARM_ISB(void) {
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ARM_MCR(p15, 0, 0, c7, c5, 4);
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}
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/*
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* A Data Memory Barrier (DMB) ensures that all explicit memory accesses before
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* the DMB instruction complete before any explicit memory accesses after the DMB instruction start.
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*/
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static inline void ARM_DMB(void) {
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ARM_MCR(p15, 0, 0, c7, c10, 5);
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}
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/* Wait For Interrupt */
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static inline void ARM_WFI(void) {
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asm_v("wfi\n\t");
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}
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/* Wait For Event */
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static inline void ARM_WFE(void) {
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asm_v("wfe\n\t");
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}
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/* Send Event */
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static inline void ARM_SEV(void) {
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asm_v("sev\n\t");
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}
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/* Auxiliary Control Registers */
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static inline u32 ARM_GetACR(void) {
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u32 acr;
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ARM_MRC(p15, 0, acr, c1, c0, 1);
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return acr;
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}
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static inline void ARM_SetACR(u32 acr) {
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ARM_MCR(p15, 0, acr, c1, c0, 1);
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}
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void ARM_ISB(void);
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void ARM_DMB(void);
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void ARM_WFI(void);
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void ARM_WFE(void);
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void ARM_SEV(void);
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u32 ARM_GetACR(void);
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void ARM_SetACR(u32 acr);
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#endif
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// Data Synchronization Barrier
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void ARM_DSB(void);
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/*
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* A Data Synchronization Barrier (DSB) completes when all
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* instructions before this instruction complete.
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*/
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static inline void ARM_DSB(void) {
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ARM_MCR(p15, 0, 0, c7, c10, 4);
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}
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// Get and set Control Register
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u32 ARM_GetCR(void);
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void ARM_SetCR(u32 cr);
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// Get and set Thread ID
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u32 ARM_GetTID(void);
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void ARM_SetTID(u32 tid);
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/* Control Registers */
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static inline u32 ARM_GetCR(void) {
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u32 cr;
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ARM_MRC(p15, 0, cr, c1, c0, 0);
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return cr;
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}
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// Core ID (not CPU ID)
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u32 ARM_CoreID(void);
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static inline void ARM_SetCR(u32 cr) {
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ARM_MCR(p15, 0, cr, c1, c0, 0);
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}
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// Get and set CPSR
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u32 ARM_GetCPSR(void);
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void ARM_SetCPSR_c(u32 sr);
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/* Thread ID Registers */
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static inline u32 ARM_GetTID(void) {
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u32 pid;
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#ifdef ARM9
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ARM_MRC(p15, 0, pid, c13, c0, 1);
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#else
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ARM_MRC(p15, 0, pid, c13, c0, 4);
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#endif
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return pid;
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}
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// Manage interrupts
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void ARM_DisableInterrupts(void);
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void ARM_EnableInterrupts(void);
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u32 ARM_EnterCritical(void);
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void ARM_LeaveCritical(u32 stat);
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static inline void ARM_SetTID(u32 pid) {
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#ifdef ARM9
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ARM_MCR(p15, 0, pid, c13, c0, 1);
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#else
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ARM_MCR(p15, 0, pid, c13, c0, 4);
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#endif
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}
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/* CPU ID */
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static inline u32 ARM_CoreID(void) {
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u32 id;
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#ifdef ARM9
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id = 0;
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#else
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ARM_MRC(p15, 0, id, c0, c0, 5);
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#endif
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return id & 3;
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}
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/* Status Register */
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static inline u32 ARM_GetCPSR(void) {
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u32 sr;
|
||||
ARM_MRS(sr, cpsr);
|
||||
return sr;
|
||||
}
|
||||
|
||||
static inline void ARM_SetCPSR_c(u32 sr) {
|
||||
ARM_MSR(cpsr_c, sr);
|
||||
}
|
||||
|
||||
static inline void ARM_DisableInterrupts(void) {
|
||||
#ifdef ARM9
|
||||
ARM_SetCPSR_c(ARM_GetCPSR() | SR_NOINT);
|
||||
#else
|
||||
ARM_CPSID(if);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void ARM_EnableInterrupts(void) {
|
||||
#ifdef ARM9
|
||||
ARM_SetCPSR_c(ARM_GetCPSR() & ~SR_NOINT);
|
||||
#else
|
||||
ARM_CPSIE(if);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline u32 ARM_EnterCritical(void) {
|
||||
u32 stat = ARM_GetCPSR();
|
||||
ARM_DisableInterrupts();
|
||||
return stat & SR_NOINT;
|
||||
}
|
||||
|
||||
static inline void ARM_LeaveCritical(u32 stat) {
|
||||
ARM_SetCPSR_c((ARM_GetCPSR() & ~SR_NOINT) | stat);
|
||||
}
|
||||
|
||||
|
||||
/* Cache functions */
|
||||
static inline void ARM_InvIC(void) {
|
||||
#ifdef ARM9
|
||||
ARM_MCR(p15, 0, 0, c7, c5, 0);
|
||||
#else
|
||||
ARM_MCR(p15, 0, 0, c7, c7, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void ARM_InvIC_Range(void *base, u32 len) {
|
||||
u32 addr = (u32)base & ~0x1F;
|
||||
len >>= 5;
|
||||
|
||||
do {
|
||||
#ifdef ARM9
|
||||
ARM_MCR(p15, 0, addr, c7, c5, 1);
|
||||
#else
|
||||
ARM_MCR(p15, 0, addr, c7, c7, 1);
|
||||
#endif
|
||||
addr += 0x20;
|
||||
} while(len--);
|
||||
}
|
||||
|
||||
static inline void ARM_InvDC(void) {
|
||||
ARM_MCR(p15, 0, 0, c7, c6, 0);
|
||||
}
|
||||
|
||||
static inline void ARM_InvDC_Range(void *base, u32 len) {
|
||||
u32 addr = (u32)base & ~0x1F;
|
||||
len >>= 5;
|
||||
|
||||
do {
|
||||
ARM_MCR(p15, 0, addr, c7, c6, 1);
|
||||
addr += 0x20;
|
||||
} while(len--);
|
||||
}
|
||||
|
||||
static inline void ARM_WbDC(void) {
|
||||
#ifdef ARM9
|
||||
u32 seg = 0, ind;
|
||||
do {
|
||||
ind = 0;
|
||||
do {
|
||||
ARM_MCR(p15, 0, seg | ind, c7, c10, 2);
|
||||
ind += 0x20;
|
||||
} while(ind < 0x400);
|
||||
seg += 0x40000000;
|
||||
} while(seg != 0);
|
||||
#else
|
||||
ARM_MCR(p15, 0, 0, c7, c10, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void ARM_WbDC_Range(void *base, u32 len) {
|
||||
u32 addr = (u32)base & ~0x1F;
|
||||
len >>= 5;
|
||||
|
||||
do {
|
||||
ARM_MCR(p15, 0, addr, c7, c10, 1);
|
||||
addr += 0x20;
|
||||
} while(len--);
|
||||
}
|
||||
|
||||
static inline void ARM_WbInvDC(void) {
|
||||
#ifdef ARM9
|
||||
u32 seg = 0, ind;
|
||||
do {
|
||||
ind = 0;
|
||||
do {
|
||||
ARM_MCR(p15, 0, seg | ind, c7, c14, 2);
|
||||
ind += 0x20;
|
||||
} while(ind < 0x400);
|
||||
seg += 0x40000000;
|
||||
} while(seg != 0);
|
||||
#else
|
||||
ARM_MCR(p15, 0, 0, c7, c14, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void ARM_WbInvDC_Range(void *base, u32 len) {
|
||||
u32 addr = (u32)base & ~0x1F;
|
||||
len >>= 5;
|
||||
|
||||
do {
|
||||
ARM_MCR(p15, 0, addr, c7, c14, 1);
|
||||
addr += 0x20;
|
||||
} while(len--);
|
||||
}
|
||||
void ARM_InvIC(void);
|
||||
void ARM_InvIC_Range(void *base, u32 len);
|
||||
void ARM_InvDC(void);
|
||||
void ARM_InvDC_Range(void *base, u32 len);
|
||||
void ARM_WbDC(void);
|
||||
void ARM_WbDC_Range(void *base, u32 len);
|
||||
void ARM_WbInvDC(void);
|
||||
void ARM_WbInvDC_Range(void *base, u32 len);
|
||||
|
||||
static inline void ARM_BKPT(void) {
|
||||
__builtin_trap();
|
||||
|
||||
@ -59,7 +59,10 @@
|
||||
(!!(x) ? (void)0 : __builtin_trap())
|
||||
|
||||
static inline void waitClks(unsigned clk) {
|
||||
asm_v("1: subs %0, %0, #2\n\tbne 1b\n\t":"=r"(clk)::"memory","cc");
|
||||
clk >>= 1;
|
||||
while(clk--) {
|
||||
asm_v("nop":::"memory", "cc");
|
||||
}
|
||||
}
|
||||
|
||||
#define STATIC_ASSERT(...) \
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user